Triple-Speed Ethernet (TSE) data path reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel® FPGA, and to observe live network traffic flowing through a loop-back Ethernet cable or a Gigabit Ethernet switch. This design also helps you to verify your Ethernet-based system operation with an Intel University of New Hampshire (UNH) verified TSE function and a standard off-the-shelf Ethernet PHY device. You can leverage this design to build your own Ethernet system with low risk and minimal effort.
The reference design is built with Altera's SOPC Builder using two instances of the TSE MegaCore® function in a Stratix® II GX FPGA and two of the serial transceivers in the FPGA. This reference design demonstrates the operation of the TSE MegaCore function up to the maximum wire-speed performance in loop-back hardware configuration.
- Showcases two instances of the TSE MegaCore function supporting 10/100/1000 Mbps Ethernet operations in SGMII mode with auto-negotiation
- Demonstrates sending, receiving, and automatic checking of Ethernet packets up to the maximum theoretical data rates of 10/100/1000 Mbps
- Jump-starts your embedded system design/performance evaluation
- Minimal hardware requirements: Stratix II GX PCI Express development kit, two small form pluggable (SFP) modules, Ethernet copper loop-back cable assembly, a host computer, and an Intel FPGA Download Cable or Intel FPGA Parallel Port Cable assembly
- Programmable settings include number of packets, packet length, payload data type, and source and destination MAC addresses
- Step-by-step walk-through instructions, complete design files (including Quartus® II archive) and Windows XP-based software application for test control and monitoring are provided
Demonstrated Intel Technology
- Stratix II GX FPGAs
- TSE MegaCore function
- Nios® II embedded processor intellectual property (IP) cores
- Nios II Embedded Design Suite (EDS)
- SOPC Builder
- Avalon® system interconnect fabric