FIR II Intel® FPGA IP Core

The Intel® FIR II IP core provides a fully-integrated finite impulse response (FIR) filter function optimized for use with Altera FPGA devices. The II IP core has an interactive parameter editor that allows you to easily create custom FIR filters. The parameter editor outputs IP functional simulation model files for use with Verilog HDL and VHDL simulators. You can use the parameter editor to implement a variety of filter types, including single rate, decimation, interpolation, and fractional rate filters.

Many digital systems use signal filtering to remove unwanted noise, to provide spectral shaping, or to perform signal detection or analysis. FIR filters and infinite impulse response (IIR) filters provide these functions. Typical filter applications include signal preconditioning, band selection, and low-pass filtering.

  • Exploiting maximal designs efficiency through hardware optimizations such as:
    • Interpolation
    • Decimation
    • Symmetry
    • Decimation half-band
    • Time sharing
  • Easy system integration using Avalon® Streaming (Avalon-ST) interfaces.
  • Memory and multiplier trade-offs to balance the implementation between logic elements (LEs) and memory blocks (M512, M4K, M9K, M10K, M20K, or M144K).
  • Support for run-time coefficient reloading capability and multiple coefficient banks.
  • User-selectable output precision via truncation, saturation, and rounding.

For technical support on this IP core, please visit Intel® Premier Support. You can also search for related topics on this function in the Knowledge Center.