ecc_hmc_ocp_slv_block Address Map

Module Instance Base Address End Address
ecc_hmc_ocp_slv_block 0xFFCFB000 0xFFCFDFFF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
IP_REV_ID 0x0 32 RO 0x0 
IP_REV_ID
DDRIOCTRL 0x08 32 RW 0x0 
DDR IO Control Register
DDRCALSTAT 0x00C 32 RO 0x0 
DDR Calibration Register
MPR_0BEAT1 0x010 32 RO 0x0 
MPR register [31:0] for first beat
MPR_1BEAT1 0x014 32 RO 0x0 
MPR register [63:32] for first beat
MPR_2BEAT1 0x018 32 RO 0x0 
MPR register [95:64] for first beat
MPR_3BEAT1 0x01C 32 RO 0x0 
MPR register [127:96] for first beat
MPR_4BEAT1 0x020 32 RO 0x0 
MPR register [159:128] for first beat
MPR_5BEAT1 0x024 32 RO 0x0 
MPR register [191:160] for first beat
MPR_6BEAT1 0x028 32 RO 0x0 
MPR register [223:192] for first beat
MPR_7BEAT1 0x02C 32 RO 0x0 
MPR register [255:224] for first beat
MPR_8BEAT1 0x030 32 RO 0x0 
MPR register [287:256] for first beat
MPR_0BEAT2 0x034 32 RO 0x0 
MPR register [31:0] for second beat
MPR_1BEAT2 0x038 32 RO 0x0 
MPR register [63:32] for second beat
MPR_2BEAT2 0x03C 32 RO 0x0 
MPR register [95:64] for second beat
MPR_3BEAT2 0x040 32 RO 0x0 
MPR register [127:96] for second beat
MPR_4BEAT2 0x044 32 RO 0x0 
MPR register [159:128] for second beat
MPR_5BEAT2 0x048 32 RO 0x0 
MPR register [191:160] for second beat
MPR_6BEAT2 0x04C 32 RO 0x0 
MPR register [223:192] for second beat
MPR_7BEAT2 0x050 32 RO 0x0 
MPR register [255:224] for second beat
MPR_8BEAT2 0x054 32 RO 0x0 
MPR register [287:256] for second beat
AUTO_PRECHARGE 0x60 32 RW 0x0 
auto-precharge bit
ECCCTRL1 0x100 32 RW 0x0 
ECC control 1.
This bit is used to set the initialize the memory and ecc to a known value
ECCCTRL2 0x104 32 RW 0x0 
ECC control 2.
This bit is used to set the initialize the memory and ecc to a known value
ERRINTEN 0x110 32 RW 0x0 
Error Interrupt enable
ERRINTENS 0x114 32 RW 0x0 
Error Interrupt set
ERRINTENR 0x118 32 RW 0x0 
Error Interrupt reset.
INTMODE 0x11C 32 RW 0x0 
Interrupt mode
INTSTAT 0x120 32 RW 0x0 
Interrupt status
DIAGINTTEST 0x124 32 RW 0x0 
Enable diagnostic errors
MODSTAT 0x128 32 RW 0x0 
Counter feature status flag
DERRADDRA 0x12C 32 RO 0x0 
Double-bit error address
SERRADDRA 0x130 32 RO 0x0 
Single-bit error address
AUTOWB_CORRADDR 0x138 32 RO 0x0 
This register shows the address of the current autoWB correction SBE.
SERRCNTREG 0x13C 32 RW 0x0 
Maximum counter value for single-bit error interrupt
AUTOWB_DROP_CNTREG 0x140 32 RW 0x1 
Maximum counter value for AUTOWB correction interrupt
ECC_REG2WRECCDATABUS 0x144 32 RW 0x0 
ECC from register associated to data which will be written to the RAM
ECC_RDECCDATA2REGBUS 0x148 32 RO 0x0 
ECC of data from RAM will be written to register
ECC_REG2RDECCDATABUS 0x14C 32 RW 0x0 
ECC from register associated to RD data which will be written to hmc ecc
ECC_DIAGON 0x150 32 RW 0x0 
Enable diagnostics access
ECC_DECSTAT 0x154 32 RW 0x0 
Diagnostic decoder status
ECC_ERRGENADDR_0 0x160 32 RO 0x0 
Error address register
ECC_ERRGENADDR_1 0x164 32 RO 0x0 
Error address register
ECC_ERRGENADDR_2 0x168 32 RO 0x0 
Error address register
ECC_ERRGENADDR_3 0x16C 32 RO 0x0 
Error address register
ECC_REG2RDDATABUS_BEAT0 0x170 32 RW 0x0 
ECC Reg2Rddatabus_beat0
ECC_REG2RDDATABUS_BEAT1 0x174 32 RW 0x0 
ECC Reg2Rddatabus_beat1
ECC_REG2RDDATABUS_BEAT2 0x178 32 RW 0x0 
ECC Reg2Rddatabus_beat2
ECC_REG2RDDATABUS_BEAT3 0x17C 32 RW 0x0 
ECC Reg2Rddatabus_beat3