rf_ctrl_config Address Map

Module Instance Base Address End Address
i_nand__reg_apb__10b80000__rf_ctrl_config__SEG_L4_MP_nand_s_0x0_0x10000 0x10B80400 0x10B80497
Register Offset Width Access Reset Value Description
transfer_cfg_0 0x0 32 RW 0x00000001 
            Transfer config 0 register. It is utilized to configure data transfer parameters.
            Value of this register is valid only for command type of program pages and
            read pages. For other commands transfer size parameters are
            selected automatically according to chosen command type.
transfer_cfg_1 0x4 32 RW 0x10001000 
            Transfer config 1 register. It is utilized to configure data transfer parameters.
            Value of this register is valid only for command type of program pages,
            read pages and copyback. For other commands transfer size parameters are
            selected automatically according to chosen command.
long_polling 0x8 32 RO 0x000003E8 
Wait count value for long polling.
short_polling 0xC 32 RO 0x000001F4 
Status monitor cycle count value.
rdst_ctrl_0 0x10 32 RW 0x40400001 
Device ready status control register.
rdst_ctrl_1 0x14 32 RW 0x41410000 
Operation status control register. Controller doesn't apply any implicit checks, so host needs to unmask all status bits that need to be checked to detect error condition
lun_status_cmd 0x18 32 RO 0x00000000 
Indicates the command to be sent while checking status of the next LUN.
lun_interleaved_cmd 0x1C 32 RO 0x00000000 
Interleaved commands support.
lun_addr_offset 0x20 32 RO 0x00000000 
Indicates the starting address of next LUN.
nf_dev_layout 0x24 32 RW 0x00100000 
NF device layout.
ecc_config_0 0x28 32 RO 0x00000000 
ECC engine configuration register 0.
ecc_config_1 0x2C 32 RO 0x00000000 
Erase detection config register
device_ctrl 0x30 32 RO 0x00000010 
Device control register.
multiplane_config 0x34 32 RO 0x00000000 
Multiplane settings register. The Address part of sequence is described using three symbols: col_addr - it means column address only, row_addr - it means row address only, addr - it means both row and column address
cache_config 0x38 32 RO 0x00000000 
This register contains enable flags for cache operations.
dma_settings 0x3C 32 RO 0x00000000 
DMA settings register. It is common register for both Master and Slave interface.
sdma_size 0x40 32 RO 0x00000000 
Transferred data block size for the Slave DMA module.
sdma_trd_num 0x44 32 RO 0x00000000 
Thread number associated with transferred data block for the Slave DMA module.
time_out 0x48 32 RW 0xFFFFFFFF 
This register configures time out delay
sdma_addr0 0x4C 32 RO 0x00000000 
            This register stores the buffer address in the host memory that is used as a sink/source for the SDMA transfer.
            The SDMA address is based on the Memory Pointer field that was programed by the host as part of the CDMA/PIO command.
            A single CDMA/PIO command can trigger multiple transfers on the slave interface, so the SDMA address value is automatically incremented and updated before
            each SDMA transfer.
sdma_addr1 0x50 32 RO 0x00000000 
            This register stores the buffer address in the host memory that is used as a sink/source for the SDMA transfer.
            The SDMA address is based on the Memory Pointer field that was programed by the host as part of the CDMA/PIO command.
            A single CDMA/PIO command can trigger multiple transfers on the slave interface, so the SDMA address value is automatically incremented and updated before
            each SDMA transfer.
fifo_trigg_level 0x54 32 RW 0x00000000 
            This register stores the trigger level value for TX FIFO and single package size for the DMA module.
            If value of field dma_package_size is other than 0 data transfer on system
            interface starts after there is fifo_trigg_lvl number of data (for read transfer)
            or available space (in case of write transfer) in FIFO.
            Transmission is invoked for single package which size is determined by value
            of the dma_package_size field.
remap_ctrl 0x80 32 RO 0x00000000 
This register controls the Remap mechanism.
remap_mask 0x84 32 RW 0xFFFFFFFF 
Remap mask mechanism.
remap_access 0x88 32 RO 0x00000000 
Register utilized to access the Records Table.
remap_log_addr 0x8C 32 RW 0x00000000 
Register with logical address of the remap record.
remap_phys_addr 0x90 32 RW 0x00000000 
Register with physical address of the remap record.
control_data_ctrl 0x94 32 RO 0x00000000 
            Register configures control-data part of
            transferred data block. Value of this register is valid only
            for command type of program pages, read pages and
            copyback. For other commands transfer size parameters are
            selected automatically according to chosen
            command.