device_ctrl 

         Device control register.
Module Instance Base Address Register Address
i_nand__reg_apb__10b80000__rf_ctrl_config__SEG_L4_MP_nand_s_0x0_0x10000 0x10B80400 0x10B80430

Size: 32

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_9

RO 0x0

pslc_prefix_cmd

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_8

RO 0x0

pslc_prefix_sel

RW 0x0

Reserved_7

RO 0x0

row_addr_width

RW 0x0

pslc_prefix_en

RW 0x0

chrc_wdth

RW 0x0

time_out_en

RW 0x1

cont_on_err

RW 0x0

Reserved_2

RO 0x0

Reserved

ce_hold

RW 0x0

device_ctrl Fields

Bit Name Description Access Reset
31:24 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
23:16 pslc_prefix_cmd 
              The pslc prefix command value. It is valid only when the
              pslc_prefix_sel is set to a 2'b10.
RW 0x0
15:12 Reserved_8 
Reserved bitfield added by Magillem
 RO 0x0
11:10 pslc_prefix_sel 
              Filed selects row address width. Field
              encoding is as following:[list]
              [*] 2'b00 - 8'hA2 prefix command,
              [*] 2'b01 - 8'h3B prefix command,
              [*] 2'b10 - Programmable  prefix command.
              [/list]
RW 0x0
9 Reserved_7 
Reserved bitfield added by Magillem
 RO 0x0
8:7 row_addr_width 
              Filed selects row address width. Field
              encoding is as following:[list]
              [*] 2'b00 - three bytes row address,
              [*] 2'b01 - two bytes row address,
              [*] 2'b10 - four bytes row address.
              [/list]
RW 0x0
6 pslc_prefix_en 
              Bit used to enable/disable the prefix command sending
              for the TLC devices working in the pSLC mode
RW 0x0
5 chrc_wdth 
If this bit is cleared then controller
            will use the change read column sequence with column address
            only. When it is set then controller will use the change
            read column sequence with full address
            (row+column).
 RW 0x0
4 time_out_en 
If this bit is set then Command Engine
            time out mechanism is enabled.
 RW 0x1
3 cont_on_err 
If this bit is cleared and any operation
            programed by descriptor fails, then controller will drop
            current descriptors chain execution. When it is set
            description execution is continued. Thread Reset
            command occurrence breaks descriptor chain regardless of
            this bit.
 RW 0x0
2 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
1 Reserved 
Reserved
 RW 0x0
0 ce_hold 
If this field is set then CE bus state
            is preserved between commands. Some devices may require to keep the CE# low through the whole SetFeature
            sequence. ce_hold can be used for this purpose also.
 RW 0x0