long_polling

         Wait count value for long polling.


Module Instance	Base Address	Register Address
`i_nand__reg_apb__10b80000__rf_ctrl_config__SEG_L4_MP_nand_s_0x0_0x10000`	`0x10B80400`	`0x10B80408`

Size: 32

Offset: 0x8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`long_polling` `RW 0x3E8`

long_polling Fields

Bit Name Description Access Reset

31:16

Bit	Name	Description	Access	Reset
31:16	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
15:0	`long_polling`	Number of system clock cycles after issue of erase/write/read operation before the controller starts to poll for status. This value is valid only in the status polling mode. First polling will happen after this many number of system clock cycles. Then on polling will happen every short_polling cycles. The long polling value should be significantly larger the short polling value.	`RW`	`0x3E8`

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

15:0

long_polling

Number of system clock cycles after issue of erase/write/read operation before the controller starts to poll for status. This value is valid only in the status polling mode. First polling will happen after this many number of system clock cycles. Then on polling will happen every short_polling cycles. The long polling value should be significantly larger the short polling value.

RW

0x3E8