cache_config

         This register contains enable flags for cache operations.


Module Instance	Base Address	Register Address
`i_nand__reg_apb__10b80000__rf_ctrl_config__SEG_L4_MP_nand_s_0x0_0x10000`	`0x10B80400`	`0x10B80438`

Size: 32

Offset: 0x38

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_2` `RO 0x0`														`cache_wr_en` `RW 0x0`	`cache_rd_en` `RW 0x0`

cache_config Fields


Bit	Name	Description	Access	Reset
31:2	`Reserved_2`	Reserved bitfield added by Magillem	`RO`	`0x0`
1	`cache_wr_en`	This bit enables cache write command sequences support.	`RW`	`0x0`
0	`cache_rd_en`	This bit enables cache read command sequences support.	`RW`	`0x0`