rf_ctrl_config Summary

Base Address: 0x10B80400


Register Address Offset	Bit Fields
`i_nand__reg_apb__10b80000__rf_ctrl_config__SEG_L4_MP_nand_s_0x0_0x10000`
`transfer_cfg_0` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`offset` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`sector_cnt` `RW 0x1`
`transfer_cfg_1` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`last_sector_size` `RW 0x1000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sector_size` `RW 0x1000`
`long_polling` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`long_polling` `RW 0x3E8`
`short_polling` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`short_polling` `RW 0x1F4`
`rdst_ctrl_0` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ready_mask` `RW 0x40`								`ready_value` `RW 0x40`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`rb_enable` `RW 0x1`
`rdst_ctrl_1` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`error_mask` `RW 0x41`								`error_value` `RW 0x41`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`lun_status_cmd` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`lun_stat_sel` `RW 0x0`
`lun_interleaved_cmd` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`									`program_after_read` `RW 0x0`	`Reserved_1` `RO 0x0`				`lun_col_cmd` `RW 0x0`
`lun_addr_offset` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`											`lun_addr_offset` `RW 0x0`
`nf_dev_layout` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`blk_addr_idx` `RW 0x0`					`Reserved_3` `RO 0x0`			`LN` `RW 0x1`				`Reserved_2` `RO 0x0`			`lun_en` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PPB` `RW 0x0`
`ecc_config_0` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`					`corr_str` `RW 0x0`			`Reserved_3` `RO 0x0`			`scrambler_en` `RW 0x0`	`Reserved_2` `RO 0x0`		`erase_det_en` `RW 0x0`	`ecc_enable` `RW 0x0`
`ecc_config_1` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`erase_det_lvl` `RW 0x0`
`device_ctrl` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`								`pslc_prefix_cmd` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`				`pslc_prefix_sel` `RW 0x0`		`Reserved_7` `RO 0x0`	`row_addr_width` `RW 0x0`		`pslc_prefix_en` `RW 0x0`	`chrc_wdth` `RW 0x0`	`time_out_en` `RW 0x1`	`cont_on_err` `RW 0x0`	`Reserved_2` `RO 0x0`	`Reserved`	`ce_hold` `RW 0x0`
`multiplane_config` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`					`pl_status_en` `RW 0x0`	`last_wr_cmd` `RW 0x0`	`mpl_erase_seq` `RW 0x0`	`mpl_rd_seq` `RW 0x0`			`Reserved_5` `RO 0x0`			`mpl_prg_seq` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`					`mpl_pl_num` `RW 0x0`			`Reserved_3` `RO 0x0`			`mpl_cpbk_rd_seq` `RW 0x0`	`Reserved_2` `RO 0x0`		`mpl_wr_en` `RW 0x0`	`mpl_rd_en` `RW 0x0`
`cache_config` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`														`cache_wr_en` `RW 0x0`	`cache_rd_en` `RW 0x0`
`dma_settings` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`														`sdma_err_rsp` `RW 0x0`	`OTE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`burst_sel` `RW 0x0`
`sdma_size` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`sdma_size` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdma_size` `RO 0x0`
`sdma_trd_num` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`													`sdma_trd` `RO 0x0`
`time_out` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`time_out_val` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`time_out_val` `RW 0xFFFFFFFF`
`sdma_addr0` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`sdma_addr_l` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdma_addr_l` `RO 0x0`
`sdma_addr1` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`sdma_addr_h` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdma_addr_h` `RO 0x0`
`fifo_trigg_level` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`dma_package_size` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`fifo_trigg_lvl` `RW 0x0`
`remap_ctrl` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`					`rec_cnt` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`rmp_en` `RW 0x0`
`remap_mask` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`remap_mask` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`remap_mask` `RW 0xFFFFFFFF`
`remap_access` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`						`rec_rd_idx` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`				`rec_trg` `RW 0x0`				`rec_di_err` `RW 0x0`	`Reserved_2` `RO 0x0`				`rec_actype` `RW 0x0`		`rec_access` `RW 0x0`
`remap_log_addr` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`remap_log_addr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`remap_log_addr` `RW 0x0`
`remap_phys_addr` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`remap_phys_addr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`remap_phys_addr` `RW 0x0`
`control_data_ctrl` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`control_data_size` `RW 0x0`