intreg Address Map

Internal register map
Module Instance Base Address End Address
i_usbotg_0__usb_csr__10b00000__DWC_otg_intreg__SEG_L4_AHB_USB0_0x0_0x40000 0x10B00000 0x10B00EFF
Register Offset Width Access Reset Value Description
GOTGCTL 0x0 32 RW 0x00010000 
OTG Control and Status Register
GOTGINT 0x4 32 RW 0x00000000 
OTG Interrupt Register
GAHBCFG 0x8 32 RW 0x00000000 
AHB Configuration Register
GUSBCFG 0xC 32 RW 0x00001410 
USB Configuration Register
GRSTCTL 0x10 32 RW 0x80000000 
Reset Register
GINTSTS 0x14 32 RW 0x14000020 
Interrupt Register
GINTMSK 0x18 32 RW 0x00000000 
Interrupt Mask Register
GRXSTSR 0x1C 32 RO 0x00000000 
Receive Status Debug Read Register
GRXSTSP 0x20 32 RO 0x00000000 
Receive Status Read /Pop Register
GRXFSIZ 0x24 32 RW 0x00002000 
Receive FIFO Size Register
GNPTXFSIZ 0x28 32 RW 0x20002000 
Non-periodic Transmit FIFO Size Register
GNPTXSTS 0x2C 32 RO 0x00082000 
Non-periodic Transmit FIFO/Queue Status Register
GPVNDCTL 0x34 32 RW 0x00000000 
PHY Vendor Control Register
GGPIO 0x38 32 RW 0x00000000 
General Purpose Input/Output Register
GUID 0x3C 32 RW 0x12345678 
User ID Register
GSNPSID 0x40 32 RO 0x4F54330A 
Synopsys ID Register
GHWCFG1 0x44 32 RO 0x00000000 
User HW Config1 Register
GHWCFG2 0x48 32 RO 0x238FFC90 
User HW Config2 Register
GHWCFG3 0x4C 32 RO 0x1F8002E8 
User HW Config3 Register
GHWCFG4 0x50 32 RO 0xFE0F0020 
User HW Config4 Register
GDFIFOCFG 0x5C 32 RW 0x1F802000 
Global DFIFO Configuration Register
HPTXFSIZ 0x100 32 RW 0x20004000 
Host Periodic Transmit FIFO Size Register
DIEPTXF1 0x104 32 RW 0x20004000 
Device IN Endpoint Transmit FIFO Size Register 1
DIEPTXF2 0x108 32 RW 0x20006000 
Device IN Endpoint Transmit FIFO Size Register 2
DIEPTXF3 0x10C 32 RW 0x20008000 
Device IN Endpoint Transmit FIFO Size Register 3
DIEPTXF4 0x110 32 RW 0x2000A000 
Device IN Endpoint Transmit FIFO Size Register 4
DIEPTXF5 0x114 32 RW 0x2000C000 
Device IN Endpoint Transmit FIFO Size Register 5
DIEPTXF6 0x118 32 RW 0x2000E000 
Device IN Endpoint Transmit FIFO Size Register 6
DIEPTXF7 0x11C 32 RW 0x20000000 
Device IN Endpoint Transmit FIFO Size Register 7
DIEPTXF8 0x120 32 RW 0x20002000 
Device IN Endpoint Transmit FIFO Size Register 8
DIEPTXF9 0x124 32 RW 0x20004000 
Device IN Endpoint Transmit FIFO Size Register 9
DIEPTXF10 0x128 32 RW 0x20006000 
Device IN Endpoint Transmit FIFO Size Register 10
DIEPTXF11 0x12C 32 RW 0x20008000 
Device IN Endpoint Transmit FIFO Size Register 11
DIEPTXF12 0x130 32 RW 0x2000A000 
Device IN Endpoint Transmit FIFO Size Register 12
DIEPTXF13 0x134 32 RW 0x2000C000 
Device IN Endpoint Transmit FIFO Size Register 13
DIEPTXF14 0x138 32 RW 0x2000E000 
Device IN Endpoint Transmit FIFO Size Register 14
DIEPTXF15 0x13C 32 RW 0x20000000 
Device IN Endpoint Transmit FIFO Size Register 15
HCFG 0x400 32 RW 0x00000200 
Host Configuration Register
HFIR 0x404 32 RW 0x0000EA60 
Host Frame Interval Register
HFNUM 0x408 32 RO 0x00003FFF 
Host Frame Number/Frame Time Remaining Register
HPTXSTS 0x410 32 RO 0x00102000 
Host Periodic Transmit FIFO/Queue Status Register
HAINT 0x414 32 RO 0x00000000 
Host All Channels Interrupt Register
HAINTMSK 0x418 32 RW 0x00000000 
Host All Channels Interrupt Mask Register
HFLBAddr 0x41C 32 RW 0x00000000 
Host Frame List Base Address Register
HPRT 0x440 32 RW 0x00000000 
Host Port Control and Status Register
HCCHAR0 0x500 32 RW 0x00000000 
Host Channel 0 Characteristics Register
HCSPLT0 0x504 32 RW 0x00000000 
Host Channel 0 Split Control Register
HCINT0 0x508 32 RW 0x00000000 
Host Channel 0 Interrupt Register
HCINTMSK0 0x50C 32 RW 0x00000000 
Host Channel 0 Interrupt Mask Register
HCTSIZ0 0x510 32 RW 0x00000000 
Host Channel 0 Transfer Size Register
HCDMA0 0x514 32 RW 0x00000000 
Host Channel 0 DMA Address Register
HCDMAB0 0x51C 32 RW 0x00000000 
Host Channel 0 DMA Buffer Address Register
HCCHAR1 0x520 32 RW 0x00000000 
Host Channel 1 Characteristics Register
HCSPLT1 0x524 32 RW 0x00000000 
Host Channel 1 Split Control Register
HCINT1 0x528 32 RW 0x00000000 
Host Channel 1 Interrupt Register
HCINTMSK1 0x52C 32 RW 0x00000000 
Host Channel 1 Interrupt Mask Register
HCTSIZ1 0x530 32 RW 0x00000000 
Host Channel 1 Transfer Size Register
HCDMA1 0x534 32 RW 0x00000000 
Host Channel 1 DMA Address Register
HCDMAB1 0x53C 32 RW 0x00000000 
Host Channel 1 DMA Buffer Address Register
HCCHAR2 0x540 32 RW 0x00000000 
Host Channel 2 Characteristics Register
HCSPLT2 0x544 32 RW 0x00000000 
Host Channel 2 Split Control Register
HCINT2 0x548 32 RW 0x00000000 
Host Channel 2 Interrupt Register
HCINTMSK2 0x54C 32 RW 0x00000000 
Host Channel 2 Interrupt Mask Register
HCTSIZ2 0x550 32 RW 0x00000000 
Host Channel 2 Transfer Size Register
HCDMA2 0x554 32 RW 0x00000000 
Host Channel 2 DMA Address Register
HCDMAB2 0x55C 32 RW 0x00000000 
Host Channel 2 DMA Buffer Address Register
HCCHAR3 0x560 32 RW 0x00000000 
Host Channel 3 Characteristics Register
HCSPLT3 0x564 32 RW 0x00000000 
Host Channel 3 Split Control Register
HCINT3 0x568 32 RW 0x00000000 
Host Channel 3 Interrupt Register
HCINTMSK3 0x56C 32 RW 0x00000000 
Host Channel 3 Interrupt Mask Register
HCTSIZ3 0x570 32 RW 0x00000000 
Host Channel 3 Transfer Size Register
HCDMA3 0x574 32 RW 0x00000000 
Host Channel 3 DMA Address Register
HCDMAB3 0x57C 32 RW 0x00000000 
Host Channel 3 DMA Buffer Address Register
HCCHAR4 0x580 32 RW 0x00000000 
Host Channel 4 Characteristics Register
HCSPLT4 0x584 32 RW 0x00000000 
Host Channel 4 Split Control Register
HCINT4 0x588 32 RW 0x00000000 
Host Channel 4 Interrupt Register
HCINTMSK4 0x58C 32 RW 0x00000000 
Host Channel 4 Interrupt Mask Register
HCTSIZ4 0x590 32 RW 0x00000000 
Host Channel 4 Transfer Size Register
HCDMA4 0x594 32 RW 0x00000000 
Host Channel 4 DMA Address Register
HCDMAB4 0x59C 32 RW 0x00000000 
Host Channel 4 DMA Buffer Address Register
HCCHAR5 0x5A0 32 RW 0x00000000 
Host Channel 5 Characteristics Register
HCSPLT5 0x5A4 32 RW 0x00000000 
Host Channel 5 Split Control Register
HCINT5 0x5A8 32 RW 0x00000000 
Host Channel 5 Interrupt Register
HCINTMSK5 0x5AC 32 RW 0x00000000 
Host Channel 5 Interrupt Mask Register
HCTSIZ5 0x5B0 32 RW 0x00000000 
Host Channel 5 Transfer Size Register
HCDMA5 0x5B4 32 RW 0x00000000 
Host Channel 5 DMA Address Register
HCDMAB5 0x5BC 32 RW 0x00000000 
Host Channel 5 DMA Buffer Address Register
HCCHAR6 0x5C0 32 RW 0x00000000 
Host Channel 6 Characteristics Register
HCSPLT6 0x5C4 32 RW 0x00000000 
Host Channel 6 Split Control Register
HCINT6 0x5C8 32 RW 0x00000000 
Host Channel 6 Interrupt Register
HCINTMSK6 0x5CC 32 RW 0x00000000 
Host Channel 6 Interrupt Mask Register
HCTSIZ6 0x5D0 32 RW 0x00000000 
Host Channel 6 Transfer Size Register
HCDMA6 0x5D4 32 RW 0x00000000 
Host Channel 6 DMA Address Register
HCDMAB6 0x5DC 32 RW 0x00000000 
Host Channel 6 DMA Buffer Address Register
HCCHAR7 0x5E0 32 RW 0x00000000 
Host Channel 7 Characteristics Register
HCSPLT7 0x5E4 32 RW 0x00000000 
Host Channel 7 Split Control Register
HCINT7 0x5E8 32 RW 0x00000000 
Host Channel 7 Interrupt Register
HCINTMSK7 0x5EC 32 RW 0x00000000 
Host Channel 7 Interrupt Mask Register
HCTSIZ7 0x5F0 32 RW 0x00000000 
Host Channel 7 Transfer Size Register
HCDMA7 0x5F4 32 RW 0x00000000 
Host Channel 7 DMA Address Register
HCDMAB7 0x5FC 32 RW 0x00000000 
Host Channel 7 DMA Buffer Address Register
HCCHAR8 0x600 32 RW 0x00000000 
Host Channel 8 Characteristics Register
HCSPLT8 0x604 32 RW 0x00000000 
Host Channel 8 Split Control Register
HCINT8 0x608 32 RW 0x00000000 
Host Channel 8 Interrupt Register
HCINTMSK8 0x60C 32 RW 0x00000000 
Host Channel 8 Interrupt Mask Register
HCTSIZ8 0x610 32 RW 0x00000000 
Host Channel 8 Transfer Size Register
HCDMA8 0x614 32 RW 0x00000000 
Host Channel 8 DMA Address Register
HCDMAB8 0x61C 32 RW 0x00000000 
Host Channel 8 DMA Buffer Address Register
HCCHAR9 0x620 32 RW 0x00000000 
Host Channel 9 Characteristics Register
HCSPLT9 0x624 32 RW 0x00000000 
Host Channel 9 Split Control Register
HCINT9 0x628 32 RW 0x00000000 
Host Channel 9 Interrupt Register
HCINTMSK9 0x62C 32 RW 0x00000000 
Host Channel 9 Interrupt Mask Register
HCTSIZ9 0x630 32 RW 0x00000000 
Host Channel 9 Transfer Size Register
HCDMA9 0x634 32 RW 0x00000000 
Host Channel 9 DMA Address Register
HCDMAB9 0x63C 32 RW 0x00000000 
Host Channel 9 DMA Buffer Address Register
HCCHAR10 0x640 32 RW 0x00000000 
Host Channel 10 Characteristics Register
HCSPLT10 0x644 32 RW 0x00000000 
Host Channel 10 Split Control Register
HCINT10 0x648 32 RW 0x00000000 
Host Channel 10 Interrupt Register
HCINTMSK10 0x64C 32 RW 0x00000000 
Host Channel 10 Interrupt Mask Register
HCTSIZ10 0x650 32 RW 0x00000000 
Host Channel 10 Transfer Size Register
HCDMA10 0x654 32 RW 0x00000000 
Host Channel 10 DMA Address Register
HCDMAB10 0x65C 32 RW 0x00000000 
Host Channel 10 DMA Buffer Address Register
HCCHAR11 0x660 32 RW 0x00000000 
Host Channel 11 Characteristics Register
HCSPLT11 0x664 32 RW 0x00000000 
Host Channel 11 Split Control Register
HCINT11 0x668 32 RW 0x00000000 
Host Channel 11 Interrupt Register
HCINTMSK11 0x66C 32 RW 0x00000000 
Host Channel 11 Interrupt Mask Register
HCTSIZ11 0x670 32 RW 0x00000000 
Host Channel 11 Transfer Size Register
HCDMA11 0x674 32 RW 0x00000000 
Host Channel 11 DMA Address Register
HCDMAB11 0x67C 32 RW 0x00000000 
Host Channel 11 DMA Buffer Address Register
HCCHAR12 0x680 32 RW 0x00000000 
Host Channel 12 Characteristics Register
HCSPLT12 0x684 32 RW 0x00000000 
Host Channel 12 Split Control Register
HCINT12 0x688 32 RW 0x00000000 
Host Channel 12 Interrupt Register
HCINTMSK12 0x68C 32 RW 0x00000000 
Host Channel 12 Interrupt Mask Register
HCTSIZ12 0x690 32 RW 0x00000000 
Host Channel 12 Transfer Size Register
HCDMA12 0x694 32 RW 0x00000000 
Host Channel 12 DMA Address Register
HCDMAB12 0x69C 32 RW 0x00000000 
Host Channel 12 DMA Buffer Address Register
HCCHAR13 0x6A0 32 RW 0x00000000 
Host Channel 13 Characteristics Register
HCSPLT13 0x6A4 32 RW 0x00000000 
Host Channel 13 Split Control Register
HCINT13 0x6A8 32 RW 0x00000000 
Host Channel 13 Interrupt Register
HCINTMSK13 0x6AC 32 RW 0x00000000 
Host Channel 13 Interrupt Mask Register
HCTSIZ13 0x6B0 32 RW 0x00000000 
Host Channel 13 Transfer Size Register
HCDMA13 0x6B4 32 RW 0x00000000 
Host Channel 13 DMA Address Register
HCDMAB13 0x6BC 32 RW 0x00000000 
Host Channel 13 DMA Buffer Address Register
HCCHAR14 0x6C0 32 RW 0x00000000 
Host Channel 14 Characteristics Register
HCSPLT14 0x6C4 32 RW 0x00000000 
Host Channel 14 Split Control Register
HCINT14 0x6C8 32 RW 0x00000000 
Host Channel 14 Interrupt Register
HCINTMSK14 0x6CC 32 RW 0x00000000 
Host Channel 14 Interrupt Mask Register
HCTSIZ14 0x6D0 32 RW 0x00000000 
Host Channel 14 Transfer Size Register
HCDMA14 0x6D4 32 RW 0x00000000 
Host Channel 14 DMA Address Register
HCDMAB14 0x6DC 32 RW 0x00000000 
Host Channel 14 DMA Buffer Address Register
HCCHAR15 0x6E0 32 RW 0x00000000 
Host Channel 15 Characteristics Register
HCSPLT15 0x6E4 32 RW 0x00000000 
Host Channel 15 Split Control Register
HCINT15 0x6E8 32 RW 0x00000000 
Host Channel 15 Interrupt Register
HCINTMSK15 0x6EC 32 RW 0x00000000 
Host Channel 15 Interrupt Mask Register
HCTSIZ15 0x6F0 32 RW 0x00000000 
Host Channel 15 Transfer Size Register
HCDMA15 0x6F4 32 RW 0x00000000 
Host Channel 15 DMA Address Register
HCDMAB15 0x6FC 32 RW 0x00000000 
Host Channel 15 DMA Buffer Address Register
DCFG 0x800 32 RW 0x08200000 
Device Configuration Register
DCTL 0x804 32 RW 0x00000002 
Device Control Register
DSTS 0x808 32 RO 0x00000002 
Device Status Register
DIEPMSK 0x810 32 RW 0x00000000 
Device IN Endpoint Common Interrupt Mask Register
DOEPMSK 0x814 32 RW 0x00000000 
Device OUT Endpoint Common Interrupt Mask Register
DAINT 0x818 32 RO 0x00000000 
Device All Endpoints Interrupt Register
DAINTMSK 0x81C 32 RW 0x00000000 
Device All Endpoints Interrupt Mask Register
DVBUSDIS 0x828 32 RW 0x000017D7 
Device VBUS Discharge Time Register
DVBUSPULSE 0x82C 32 RW 0x000005B8 
Device VBUS Pulsing Time Register
DTHRCTL 0x830 32 RW 0x0C100020 
Device Threshold Control Register
DIEPEMPMSK 0x834 32 RW 0x00000000 
Device IN Endpoint FIFO Empty Interrupt Mask Register
DIEPCTL0 0x900 32 RW 0x00008000 
Device Control IN Endpoint 0 Control Register
DIEPINT0 0x908 32 RW 0x00000080 
Device IN Endpoint 0 Interrupt Register
DIEPTSIZ0 0x910 32 RW 0x00000000 
Device IN Endpoint 0 Transfer Size Register
DIEPDMA0 0x914 32 RW 0x0 
Device IN Endpoint 0 DMA Address Register
DTXFSTS0 0x918 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 0
DIEPDMAB0 0x91C 32 RO 0x0 
Device IN Endpoint 16 Buffer Address Register
DIEPCTL1 0x920 32 RW 0x00000000 
Device Control IN Endpoint 1 Control Register
DIEPINT1 0x928 32 RW 0x00000080 
Device IN Endpoint 1 Interrupt Register
DIEPTSIZ1 0x930 32 RW 0x00000000 
Device IN Endpoint 1 Transfer Size Register
DIEPDMA1 0x934 32 RW 0x0 
Device IN Endpoint 1 DMA Address Register
DTXFSTS1 0x938 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 1
DIEPDMAB1 0x93C 32 RO 0x0 
Device IN Endpoint 1 Buffer Address Register
DIEPCTL2 0x940 32 RW 0x00000000 
Device Control IN Endpoint 2 Control Register
DIEPINT2 0x948 32 RW 0x00000080 
Device IN Endpoint 2 Interrupt Register
DIEPTSIZ2 0x950 32 RW 0x00000000 
Device IN Endpoint 2 Transfer Size Register
DIEPDMA2 0x954 32 RW 0x0 
Device IN Endpoint 2 DMA Address Register
DTXFSTS2 0x958 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 2
DIEPDMAB2 0x95C 32 RO 0x0 
Device IN Endpoint 2 Buffer Address Register
DIEPCTL3 0x960 32 RW 0x00000000 
Device Control IN Endpoint 3 Control Register
DIEPINT3 0x968 32 RW 0x00000080 
Device IN Endpoint 3 Interrupt Register
DIEPTSIZ3 0x970 32 RW 0x00000000 
Device IN Endpoint 3 Transfer Size Register
DIEPDMA3 0x974 32 RW 0x0 
Device IN Endpoint 3 DMA Address Register
DTXFSTS3 0x978 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 3
DIEPDMAB3 0x97C 32 RO 0x0 
Device IN Endpoint 3 Buffer Address Register
DIEPCTL4 0x980 32 RW 0x00000000 
Device Control IN Endpoint 4 Control Register
DIEPINT4 0x988 32 RW 0x00000080 
Device IN Endpoint 4 Interrupt Register
DIEPTSIZ4 0x990 32 RW 0x00000000 
Device IN Endpoint 4 Transfer Size Register
DIEPDMA4 0x994 32 RW 0x0 
Device IN Endpoint 4 DMA Address Register
DTXFSTS4 0x998 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 4
DIEPDMAB4 0x99C 32 RO 0x0 
Device IN Endpoint 4 Buffer Address Register
DIEPCTL5 0x9A0 32 RW 0x00000000 
Device Control IN Endpoint 5 Control Register
DIEPINT5 0x9A8 32 RW 0x00000080 
Device IN Endpoint 5 Interrupt Register
DIEPTSIZ5 0x9B0 32 RW 0x00000000 
Device IN Endpoint 5 Transfer Size Register
DIEPDMA5 0x9B4 32 RW 0x0 
Device IN Endpoint 5 DMA Address Register
DTXFSTS5 0x9B8 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 5
DIEPDMAB5 0x9BC 32 RO 0x0 
Device IN Endpoint 5 Buffer Address Register
DIEPCTL6 0x9C0 32 RW 0x00000000 
Device Control IN Endpoint 6 Control Register
DIEPINT6 0x9C8 32 RW 0x00000080 
Device IN Endpoint 6 Interrupt Register
DIEPTSIZ6 0x9D0 32 RW 0x00000000 
Device IN Endpoint 6 Transfer Size Register
DIEPDMA6 0x9D4 32 RW 0x0 
Device IN Endpoint 6 DMA Address Register
DTXFSTS6 0x9D8 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 6
DIEPDMAB6 0x9DC 32 RO 0x0 
Device IN Endpoint 6 Buffer Address Register
DIEPCTL7 0x9E0 32 RW 0x00000000 
Device Control IN Endpoint 7 Control Register
DIEPINT7 0x9E8 32 RW 0x00000080 
Device IN Endpoint 7 Interrupt Register
DIEPTSIZ7 0x9F0 32 RW 0x00000000 
Device IN Endpoint 7 Transfer Size Register
DIEPDMA7 0x9F4 32 RW 0x0 
Device IN Endpoint 7 DMA Address Register
DTXFSTS7 0x9F8 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 7
DIEPDMAB7 0x9FC 32 RO 0x0 
Device IN Endpoint 7 Buffer Address Register
DIEPCTL8 0xA00 32 RW 0x00000000 
Device Control IN Endpoint 8 Control Register
DIEPINT8 0xA08 32 RW 0x00000080 
Device IN Endpoint 8 Interrupt Register
DIEPTSIZ8 0xA10 32 RW 0x00000000 
Device IN Endpoint 8 Transfer Size Register
DIEPDMA8 0xA14 32 RW 0x0 
Device IN Endpoint 8 DMA Address Register
DTXFSTS8 0xA18 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 8
DIEPDMAB8 0xA1C 32 RO 0x0 
Device IN Endpoint 8 Buffer Address Register
DIEPCTL9 0xA20 32 RW 0x00000000 
Device Control IN Endpoint 9 Control Register
DIEPINT9 0xA28 32 RW 0x00000080 
Device IN Endpoint 9 Interrupt Register
DIEPTSIZ9 0xA30 32 RW 0x00000000 
Device IN Endpoint 9 Transfer Size Register
DIEPDMA9 0xA34 32 RW 0x0 
Device IN Endpoint 9 DMA Address Register
DTXFSTS9 0xA38 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 9
DIEPDMAB9 0xA3C 32 RO 0x0 
Device IN Endpoint 9 Buffer Address Register
DIEPCTL10 0xA40 32 RW 0x00000000 
Device Control IN Endpoint 10 Control Register
DIEPINT10 0xA48 32 RW 0x00000080 
Device IN Endpoint 10 Interrupt Register
DIEPTSIZ10 0xA50 32 RW 0x00000000 
Device IN Endpoint 10 Transfer Size Register
DIEPDMA10 0xA54 32 RW 0x0 
Device IN Endpoint 10 DMA Address Register
DTXFSTS10 0xA58 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 10
DIEPDMAB10 0xA5C 32 RO 0x0 
Device IN Endpoint 10 Buffer Address Register
DIEPCTL11 0xA60 32 RW 0x00000000 
Device Control IN Endpoint 11 Control Register
DIEPINT11 0xA68 32 RW 0x00000080 
Device IN Endpoint 11 Interrupt Register
DIEPTSIZ11 0xA70 32 RW 0x00000000 
Device IN Endpoint 11 Transfer Size Register
DIEPDMA11 0xA74 32 RW 0x0 
Device IN Endpoint 11 DMA Address Register
DTXFSTS11 0xA78 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 11
DIEPDMAB11 0xA7C 32 RO 0x0 
Device IN Endpoint 11 Buffer Address Register
DIEPCTL12 0xA80 32 RW 0x00000000 
Device Control IN Endpoint 12 Control Register
DIEPINT12 0xA88 32 RW 0x00000080 
Device IN Endpoint 12 Interrupt Register
DIEPTSIZ12 0xA90 32 RW 0x00000000 
Device IN Endpoint 12 Transfer Size Register
DIEPDMA12 0xA94 32 RW 0x0 
Device IN Endpoint 12 DMA Address Register
DTXFSTS12 0xA98 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 12
DIEPDMAB12 0xA9C 32 RO 0x0 
Device IN Endpoint 12 Buffer Address Register
DIEPCTL13 0xAA0 32 RW 0x00000000 
Device Control IN Endpoint 13 Control Register
DIEPINT13 0xAA8 32 RW 0x00000080 
Device IN Endpoint 13 Interrupt Register
DIEPTSIZ13 0xAB0 32 RW 0x00000000 
Device IN Endpoint 13 Transfer Size Register
DIEPDMA13 0xAB4 32 RW 0x0 
Device IN Endpoint 13 DMA Address Register
DTXFSTS13 0xAB8 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 13
DIEPDMAB13 0xABC 32 RO 0x0 
Device IN Endpoint 13 Buffer Address Register
DIEPCTL14 0xAC0 32 RW 0x00000000 
Device Control IN Endpoint 14 Control Register
DIEPINT14 0xAC8 32 RW 0x00000080 
Device IN Endpoint 14 Interrupt Register
DIEPTSIZ14 0xAD0 32 RW 0x00000000 
Device IN Endpoint 14 Transfer Size Register
DIEPDMA14 0xAD4 32 RW 0x0 
Device IN Endpoint 14 DMA Address Register
DTXFSTS14 0xAD8 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 14
DIEPDMAB14 0xADC 32 RO 0x0 
Device IN Endpoint 14 Buffer Address Register
DIEPCTL15 0xAE0 32 RW 0x00000000 
Device Control IN Endpoint 15 Control Register
DIEPINT15 0xAE8 32 RW 0x00000080 
Device IN Endpoint 15 Interrupt Register
DIEPTSIZ15 0xAF0 32 RW 0x00000000 
Device IN Endpoint 15 Transfer Size Register
DIEPDMA15 0xAF4 32 RW 0x0 
Device IN Endpoint 15 DMA Address Register
DTXFSTS15 0xAF8 32 RO 0x00000000 
Device IN Endpoint Transmit FIFO Status Register 15
DIEPDMAB15 0xAFC 32 RO 0x0 
Device IN Endpoint 15 Buffer Address Register
DOEPCTL0 0xB00 32 RW 0x00008000 
Device Control OUT Endpoint 0 Control Register
DOEPINT0 0xB08 32 RW 0x00000000 
Device OUT Endpoint 0 Interrupt Register
DOEPTSIZ0 0xB10 32 RW 0x00000000 
Device OUT Endpoint 0 Transfer Size Register
DOEPDMA0 0xB14 32 RW 0x0 
Device OUT Endpoint 0 DMA Address Register
DOEPDMAB0 0xB1C 32 RO 0x0 
Device OUT Endpoint 16 Buffer Address Register
DOEPCTL1 0xB20 32 RW 0x00000000 
Device Control OUT Endpoint 1 Control Register
DOEPINT1 0xB28 32 RW 0x00000000 
Device OUT Endpoint 1 Interrupt Register
DOEPTSIZ1 0xB30 32 RW 0x00000000 
Device OUT Endpoint 1 Transfer Size Register
DOEPDMA1 0xB34 32 RW 0x0 
Device OUT Endpoint 1 DMA Address Register
DOEPDMAB1 0xB3C 32 RO 0x0 
Device OUT Endpoint 1 Buffer Address Register
DOEPCTL2 0xB40 32 RW 0x00000000 
Device Control OUT Endpoint 2 Control Register
DOEPINT2 0xB48 32 RW 0x00000000 
Device OUT Endpoint 2 Interrupt Register
DOEPTSIZ2 0xB50 32 RW 0x00000000 
Device OUT Endpoint 2 Transfer Size Register
DOEPDMA2 0xB54 32 RW 0x0 
Device OUT Endpoint 2 DMA Address Register
DOEPDMAB2 0xB5C 32 RO 0x0 
Device OUT Endpoint 2 Buffer Address Register
DOEPCTL3 0xB60 32 RW 0x00000000 
Device Control OUT Endpoint 3 Control Register
DOEPINT3 0xB68 32 RW 0x00000000 
Device OUT Endpoint 3 Interrupt Register
DOEPTSIZ3 0xB70 32 RW 0x00000000 
Device OUT Endpoint 3 Transfer Size Register
DOEPDMA3 0xB74 32 RW 0x0 
Device OUT Endpoint 3 DMA Address Register
DOEPDMAB3 0xB7C 32 RO 0x0 
Device OUT Endpoint 3 Buffer Address Register
DOEPCTL4 0xB80 32 RW 0x00000000 
Device Control OUT Endpoint 4 Control Register
DOEPINT4 0xB88 32 RW 0x00000000 
Device OUT Endpoint 4 Interrupt Register
DOEPTSIZ4 0xB90 32 RW 0x00000000 
Device OUT Endpoint 4 Transfer Size Register
DOEPDMA4 0xB94 32 RW 0x0 
Device OUT Endpoint 4 DMA Address Register
DOEPDMAB4 0xB9C 32 RO 0x0 
Device OUT Endpoint 4 Buffer Address Register
DOEPCTL5 0xBA0 32 RW 0x00000000 
Device Control OUT Endpoint 5 Control Register
DOEPINT5 0xBA8 32 RW 0x00000000 
Device OUT Endpoint 5 Interrupt Register
DOEPTSIZ5 0xBB0 32 RW 0x00000000 
Device OUT Endpoint 5 Transfer Size Register
DOEPDMA5 0xBB4 32 RW 0x0 
Device OUT Endpoint 5 DMA Address Register
DOEPDMAB5 0xBBC 32 RO 0x0 
Device OUT Endpoint 5 Buffer Address Register
DOEPCTL6 0xBC0 32 RW 0x00000000 
Device Control OUT Endpoint 6 Control Register
DOEPINT6 0xBC8 32 RW 0x00000000 
Device OUT Endpoint 6 Interrupt Register
DOEPTSIZ6 0xBD0 32 RW 0x00000000 
Device OUT Endpoint 6 Transfer Size Register
DOEPDMA6 0xBD4 32 RW 0x0 
Device OUT Endpoint 6 DMA Address Register
DOEPDMAB6 0xBDC 32 RO 0x0 
Device OUT Endpoint 6 Buffer Address Register
DOEPCTL7 0xBE0 32 RW 0x00000000 
Device Control OUT Endpoint 7 Control Register
DOEPINT7 0xBE8 32 RW 0x00000000 
Device OUT Endpoint 7 Interrupt Register
DOEPTSIZ7 0xBF0 32 RW 0x00000000 
Device OUT Endpoint 7 Transfer Size Register
DOEPDMA7 0xBF4 32 RW 0x0 
Device OUT Endpoint 7 DMA Address Register
DOEPDMAB7 0xBFC 32 RO 0x0 
Device OUT Endpoint 7 Buffer Address Register
DOEPCTL8 0xC00 32 RW 0x00000000 
Device Control OUT Endpoint 8 Control Register
DOEPINT8 0xC08 32 RW 0x00000000 
Device OUT Endpoint 8 Interrupt Register
DOEPTSIZ8 0xC10 32 RW 0x00000000 
Device OUT Endpoint 8 Transfer Size Register
DOEPDMA8 0xC14 32 RW 0x0 
Device OUT Endpoint 8 DMA Address Register
DOEPDMAB8 0xC1C 32 RO 0x0 
Device OUT Endpoint 8 Buffer Address Register
DOEPCTL9 0xC20 32 RW 0x00000000 
Device Control OUT Endpoint 9 Control Register
DOEPINT9 0xC28 32 RW 0x00000000 
Device OUT Endpoint 9 Interrupt Register
DOEPTSIZ9 0xC30 32 RW 0x00000000 
Device OUT Endpoint 9 Transfer Size Register
DOEPDMA9 0xC34 32 RW 0x0 
Device OUT Endpoint 9 DMA Address Register
DOEPDMAB9 0xC3C 32 RO 0x0 
Device OUT Endpoint 9 Buffer Address Register
DOEPCTL10 0xC40 32 RW 0x00000000 
Device Control OUT Endpoint 10 Control Register
DOEPINT10 0xC48 32 RW 0x00000000 
Device OUT Endpoint 10 Interrupt Register
DOEPTSIZ10 0xC50 32 RW 0x00000000 
Device OUT Endpoint 10 Transfer Size Register
DOEPDMA10 0xC54 32 RW 0x0 
Device OUT Endpoint 10 DMA Address Register
DOEPDMAB10 0xC5C 32 RO 0x0 
Device OUT Endpoint 10 Buffer Address Register
DOEPCTL11 0xC60 32 RW 0x00000000 
Device Control OUT Endpoint 11 Control Register
DOEPINT11 0xC68 32 RW 0x00000000 
Device OUT Endpoint 11 Interrupt Register
DOEPTSIZ11 0xC70 32 RW 0x00000000 
Device OUT Endpoint 11 Transfer Size Register
DOEPDMA11 0xC74 32 RW 0x0 
Device OUT Endpoint 11 DMA Address Register
DOEPDMAB11 0xC7C 32 RO 0x0 
Device OUT Endpoint 11 Buffer Address Register
DOEPCTL12 0xC80 32 RW 0x00000000 
Device Control OUT Endpoint 12 Control Register
DOEPINT12 0xC88 32 RW 0x00000000 
Device OUT Endpoint 12 Interrupt Register
DOEPTSIZ12 0xC90 32 RW 0x00000000 
Device OUT Endpoint 12 Transfer Size Register
DOEPDMA12 0xC94 32 RW 0x0 
Device OUT Endpoint 12 DMA Address Register
DOEPDMAB12 0xC9C 32 RO 0x0 
Device OUT Endpoint 12 Buffer Address Register
DOEPCTL13 0xCA0 32 RW 0x00000000 
Device Control OUT Endpoint 13 Control Register
DOEPINT13 0xCA8 32 RW 0x00000000 
Device OUT Endpoint 13 Interrupt Register
DOEPTSIZ13 0xCB0 32 RW 0x00000000 
Device OUT Endpoint 13 Transfer Size Register
DOEPDMA13 0xCB4 32 RW 0x0 
Device OUT Endpoint 13 DMA Address Register
DOEPDMAB13 0xCBC 32 RO 0x0 
Device OUT Endpoint 13 Buffer Address Register
DOEPCTL14 0xCC0 32 RW 0x00000000 
Device Control OUT Endpoint 14 Control Register
DOEPINT14 0xCC8 32 RW 0x00000000 
Device OUT Endpoint 14 Interrupt Register
DOEPTSIZ14 0xCD0 32 RW 0x00000000 
Device OUT Endpoint 14 Transfer Size Register
DOEPDMA14 0xCD4 32 RW 0x0 
Device OUT Endpoint 14 DMA Address Register
DOEPDMAB14 0xCDC 32 RO 0x0 
Device OUT Endpoint 14 Buffer Address Register
DOEPCTL15 0xCE0 32 RW 0x00000000 
Device Control OUT Endpoint 15 Control Register
DOEPINT15 0xCE8 32 RW 0x00000000 
Device OUT Endpoint 15 Interrupt Register
DOEPTSIZ15 0xCF0 32 RW 0x00000000 
Device OUT Endpoint 15 Transfer Size Register
DOEPDMA15 0xCF4 32 RW 0x0 
Device OUT Endpoint 15 DMA Address Register
DOEPDMAB15 0xCFC 32 RO 0x0 
Device OUT Endpoint 15 Buffer Address Register
PCGCCTL 0xE00 32 RW 0x00000000 
Power and Clock Gating Control Register