GPVNDCTL 

         PHY Vendor Control Register
Module Instance Base Address Register Address
i_usbotg_0__usb_csr__10b00000__DWC_otg_intreg__SEG_L4_AHB_USB0_0x0_0x40000 0x10B00000 0x10B00034

Size: 32

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DisUlpiDrvr

RW 0x0

RESERVED

RO 0x0

VStsDone

RW 0x0

VStsBsy

RO 0x0

NewRegReq

RW 0x0

RESERVED1

RO 0x0

RegWr

RW 0x0

RegAddr

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VCtrl

RW 0x0

RegData

RW 0x0

GPVNDCTL Fields

Bit Name Description Access Reset
31 DisUlpiDrvr 
Disable ULPI Drivers (DisUlpiDrvr)
The application sets this bit when it has finished processing
the ULPI Carkit Interrupt (GINTSTS.ULPICKINT). When
set, DWC_otg disables drivers for output signals
and masks input signal For the ULPI interface. DWC_otg
clears this bit before enabling the ULPI interface.
Value Description
0x0 Enable ULPI ouput signals
0x1 Disable ULPI ouput signals
RW 0x0
30:28 RESERVED 
RESERVED
 RO 0x0
27 VStsDone 
VStatus Done (VStsDone)
The core sets this bit when the vendor control access is
done.
This bit is cleared by the core when the application sets the
New Register Request bit (bit 25).
Value Description
0x0 VStatus Done inactive
0x1 VStatus Done active
RW 0x0
26 VStsBsy 
VStatus Busy (VStsBsy)
The core sets this bit when the vendor control access is in
progress and clears this bit when done.
Value Description
0x0 VStatus Busy inactive
0x1 VStatus Busy active
RO 0x0
25 NewRegReq 
New Register Request (NewRegReq)
The application sets this bit For a new vendor control
access.
Value Description
0x0 New Register Request not active
0x1 New Register Request active
RW 0x0
24:23 RESERVED1 
RESERVED
 RO 0x0
22 RegWr 
Register Write (RegWr)
Set this bit for register writes, and clear it for register reads.
Value Description
0x0 Register Read
0x1 Register Write
RW 0x0
21:16 RegAddr 
Register Address (RegAddr)
The 6-bit PHY register address For immediate PHY Register
Set access. Set to 6'h2F For Extended PHY Register Set
access.
 RW 0x0
15:8 VCtrl 
UTMI+ Vendor Control Register Address (VCtrl)
The 4-bit register address a vendor defined 4-bit parallel
output bus. Bits 11:8 of this field are placed on
utmi_vcontrol[3:0].
ULPI Extended Register Address (ExtRegAddr)
The 6-bit PHY extended register address.
 RW 0x0
7:0 RegData 
Register Data (RegData)
Contains the write data For register write. Read data For
register read, valid when VStatus Done is Set.
 RW 0x0