GOTGINT
OTG Interrupt Register
Module Instance | Base Address | Register Address |
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i_usbotg_0__usb_csr__10b00000__DWC_otg_intreg__SEG_L4_AHB_USB0_0x0_0x40000
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0x10B00000
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0x10B00004
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Size: 32
Offset: 0x4
Access: RW
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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GOTGINT Fields
Bit | Name | Description | Access | Reset | ||||||
---|---|---|---|---|---|---|---|---|---|---|
31:21 |
RESERVED
|
RESERVED |
RO
|
0x0
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20 |
Reserved_9
|
Reserved bitfield added by Magillem |
RO
|
0x0
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19 |
DbnceDone
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Mode: Host only Debounce Done (DbnceDone) The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively).This bit can be set only by the core and the application should write 1 to clear it.
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RW
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0x0
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18 |
ADevTOUTChg
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Mode:Host and Device A-Device Timeout Change (ADevTOUTChg) The core sets this bit to indicate that the A-device has timed out WHILE waiting FOR the B-device to connect.This bit can be set only by the core and the application should write 1 to clear it.
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RW
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0x0
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17 |
HstNegDet
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Mode:Host and Device Host Negotiation Detected (HstNegDet) The core sets this bit when it detects a host negotiation request on the USB.This bit can be set only by the core and the application should write 1 to clear it.
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RW
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0x0
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16:10 |
RESERVED1
|
RESERVED |
RO
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0x0
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9 |
HstNegSucStsChng
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Mode:Host and Device Host Negotiation Success Status Change (HstNegSucStsChng) The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation Success bit of the OTG Control and Status register (GOTGCTL.HstNegScs) to check For success or failure.This bit can be set only by the core and the application should write 1 to clear it.
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RW
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0x0
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8 |
SesReqSucStsChng
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Mode:Host and Device Session Request Success Status Change (SesReqSucStsChng) The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit in the OTG Control and Status register (GOTGCTL.SesReqScs) to check For success or failure.This bit can be set only by the core and the application should write 1 to clear it.
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RW
|
0x0
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7:3 |
RESERVED2
|
RESERVED |
RO
|
0x0
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2 |
SesEndDet
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Mode:Host and Device Session End Detected (SesEndDet) The core sets this bit when the utmiotg_bvalid signal is deasserted.This bit can be set only by the core and the application should write 1 to clear it.
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RW
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0x0
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1:0 |
RESERVED3
|
RESERVED |
RO
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0x0
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