HPTXFSIZ 

         Host Periodic Transmit FIFO Size Register
Module Instance Base Address Register Address
i_usbotg_0__usb_csr__10b00000__DWC_otg_intreg__SEG_L4_AHB_USB0_0x0_0x40000 0x10B00000 0x10B00100

Size: 32

Offset: 0x100

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

PTxFSize

RW 0x2000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x0

PTxFStAddr

RW 0x4000

HPTXFSIZ Fields

Bit Name Description Access Reset
31:30 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
29:16 PTxFSize 
Host Periodic TxFIFO Depth (PTxFSize)
This value is in terms of 32-bit words.
 Minimum value is 16
 Maximum value is 32,768
The power-on reset value of this register is specified as the Largest Host
Mode Periodic Tx Data FIFO Depth. 
Programmed values must not exceed the power-on value.
 RW 0x2000
15 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
14:0 PTxFStAddr 
Host Periodic TxFIFO Start Address (PTxFStAddr)
The power-on reset value of this register is the sum of the Largest Rx Data
FIFO Depth and Largest Non-periodic Tx Data FIFO Depth 
Programmed values must not exceed the power-on value
 RW 0x4000