Intel® Stratix® 10 FPGAs & SoC FPGA

Intel® Stratix® 10 FPGAs and SoCs deliver innovative advantages in performance, power efficiency, density, and system integration. Featuring the revolutionary Intel® Hyperflex™ FPGA Architecture and built combining Intel's patented Embedded Multi-Die Interconnect Bridge (EMIB) technology, the Advanced Interface Bus (AIB), and a growing portfolio of chiplets, Intel® Stratix® 10 devices deliver up to 2X performance gains over previous-generation, high-performance FPGAs.1

See also: Intel® Stratix® 10 FPGAs Design SoftwareDesign StoreDownloadsCommunity, and Support

Intel® Stratix® 10 FPGAs & SoC FPGA

Data Center Acceleration

Unique to Intel® Stratix® 10 Devices

  • First FPGA devices to support Intel® Ultra Path Interconnect (UPI) for direct coherent connection to Intel® Xeon® Scalable processor.
  • FPGA PCIe* hard IP with configuration up to Gen4 x16 at 16 Gbps.
  • Intel® Hyperflex™ FPGA Architecture delivers up to 1 GHz performance, enabling breakthroughs in computational throughput.
  • Hardened single-precision floating-point DSP block, compliant with IEEE 754 standard, delivers GPU-class floating performance at a fraction of the power.
  • Hardened AI Tensor Block tuned for common matrix-matrix or vector-matrix multiplications in AI acceleration applications resulting in up to 143 INT8 TOPS or 286 INT4 TOPS.3
  • Secure cloud solutions using the security features.

Wireline

Bridging and Aggregation

Unique to Intel® Stratix® 10 Devices

  • fMAX over 700 MHz using the Intel® HyperFlex™ FPGA Architecture enabling 400G Ethernet.
  • 512 bit wide datapath running at 2X performance enables half-size IP compared to conventional architectures.

OTN/Data Center Interconnect

400 Gbit/s Muxponder for Metro / DCI Features

2.4 Tbit/s Switch/Muxponder for DCI

Unique to Intel® Stratix® 10 Devices

  • Heterogeneous 3D System-in-Package (SiP) integration of transceiver tiles delivers 30G backplane support with a path to 58G data rates.
  • Intel® Hyperflex™ FPGA Architecture enables 2X performance resulting in significant IP size reduction.
  • Hardened single-precision floating-point DSP block, compliant with IEEE 754 standard, delivers GPU-class floating performance at a fraction of the power.
  • Secure cloud solutions using the security features.

Radar

Unique to Intel® Stratix® 10 Devices

  • Up to 10 TFLOPS of IEEE 754 compliant single-precision floating-point performance delivers GPU class performance at a fraction of the power.
  • Cover fMAX up to 1 GHz enabling high throughput beam processing.

ASIC Prototyping and Emulation

Unique to Intel® Stratix® 10 Devices

  • Highest density enable customers to scale prototyping and emulation solution.
  • Highest I/O counts provide flexibility for design partitioning across multiple FPGAs.
  • Readback and writeback IP enhances debug productivity.

Cyber Security

Network Intrusion Detection and Prevention

Unique to Intel® Stratix® 10 Devices

  • fMAX over 900 MHz allows monitoring of all supported protocols at line rates.
  • ARM* Cortex*-A53 processor enables direct interfacing with existing IT software.
  • Partial reconfiguration and OpenCL* platform allow for easy rules updates.

Product and Performance Information

1

Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

2OpenCL* and the OpenCL* logo are trademarks of Apple Inc. used by permission by Khronos.
3

Based on internal Intel estimates.
Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.
Intel® technologies may require enabled hardware, software or service activation.
No product or component can be absolutely secure.
Results have been estimated or simulated. Your costs and results may vary.
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