Intel® FPGA IP for DDR3 SDRAM High-Performance Controller

The Intel FPGA Intellectual Property (IP) for DDR3 SDRAM High-Performance Controller provides simplified interfaces to industry-standard DDR3 SDRAM devices and modules. The Intel FPGA IP work in conjunction with the Intel FPGA ALTMEMPHY physical interface IP. These DDR3 SDRAM IP functions offer a half-rate interface to the customer application logic.

Read the Introduction to ALTMEMPHY IP user guide ›

Intel® FPGA IP for DDR3 SDRAM High-Performance Controller

Features

  • Flexible architecture
  • Industry-standard DDR3 SDRAM device and module support
  • Ability to bolt onto the Intel FPGA IP for ALTMEMPHY physical interface for a complete DDR3 SDRAM solution
  • Feature rich
  • Optional user-controlled refresh support
  • Power-up calibrated on-chip termination (OCT)
  • Integrated error correction code (ECC) functionality
  • Ease of use
  • Platform Designer (formerly Qsys) IP support
  • Optional Avalon® Memory-Mapped local interface
  • Intel FPGA IP Evaluation Mode support
  • Includes a parameter interface
  • IP functional simulation modules for use in Intel FPGA-supported VHDL and Verilog HDL simulators

The parameter editor generates a design example that instantiates an example driver and your DDR3 SDRAM high-performance controller custom variation. The design example is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.

Typical expected performance and utilization figures for Intel FPGA IP functions are provided in the DDR3 SDRAM High-Performance Controller User Guide.

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For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

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