Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core

Intel® Stratix® 10 FPGA H-Tile FPGA production devices include a configurable, hardened protocol stack for Ethernet that is compatible with the IEEE 802.3 High Speed Ethernet Standard.

Read the Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet IP Core user guide ›

Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core

Ordering Information

Ordering code

IP-ETH-HTILEHIP: Base H-tile Ethernet Hard IP

IP-ETH-HTILEKRCR: For KR/CR enablement

IP Quality Metrics

Basics

Year IP was first released

2017

First version of Intel Quartus Prime Software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Simulation model for ModelSim*- Intel FPGA Edition

Timing and/or layout constraints

Documentation with revision control

Readme file

Y

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

N/A

Software drivers provided

N

Driver OS Support

N/A

Implementation

User interface

Avalon-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Stratix 10 FPGA

Industry-standard compliance testing performed

N

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Stratix 10 MX FPGA

Interoperability reports available

N