RapidIO Intel® FPGA IP

Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II, more information can be found in the product discontinuance notification (PDN2025).

RapidIO Intel® FPGA IP

IP Quality Metrics

Basics

Year IP was first released

2009

Latest version of Intel Quartus Prime Software supported

18.1

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*-Intel FPGA Edition

    Timing and/or layout constraints

    Testbench or design example

    Documentation with revision control

    Readme file



    Yes

    Yes

    Yes

    Yes

    Yes

    No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Avalon-MM, Avalon-ST

IP-XACT metadata

No

Verification

Simulators supported

ModelSim*, VCS, Riviera-PRO, NCSim

Hardware validated

Intel Arria 10, Arria V, Intel Cyclone 10 GX, Cyclone V, Intel Stratix 10, Stratix V

Industry-standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

No

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Arria V, Intel Arria 10, Intel Cyclone 10 GX, Intel Stratix 10

Interoperability reports available

Yes