A significant portion of the wireless industry adopts the RapidIO standard as a high-speed interconnect. The RapidIO standard is typically used between digital signal processors as well as between the control plane processors and memory. RapidIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical media attachment (PMA), such as XAUI or CEI for up to 6.25 Gbaud data rate. Intel® FPGAs are also capable of supporting RapidIO Gen3 data rates.
- PHY based on embedded transceivers
- Easy to use
- Intellectual property (IP) parameter editor allows easy manual optimization of parameters, such as interface FIFO depths, address translation windows, output differential voltage, and pre-emphasis
- Easy configuration provides ways to reduce resource utilization to create smaller Intel® FPGA IP function variations depending on application needs
- Platform Designer for system interconnect
- Robust solution
- Endpoint IP core, testbenches with proven interoperability with leading digital signal processor and switch vendors
- Compliant to RapidIO specification, Revision 1.3 / 2.1 and 2.2
For a system-level integration-ready solution, you can save several months of design time by selecting all RapidIO layers—including features, such as address translation as well as simple Avalon® Memory-Mapped (Avalon-MM) and Avalon® Streaming (Avalon-ST) FIFO interfaces.