The Platform Designer is the next-generation system integration tool in the Intel® Quartus® Prime Software. The Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. The Platform Designer utilizes a powerful hierarchical framework to offer fast response times for interconnecting large systems, while also providing support for blackbox entities. This enables the Platform Designer to provide fast response times while opening systems and creating new connections by regenerating or operating on IP blocks that have changed. The new Platform Designer tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.
The Platform Designer in the Intel Quartus Prime Pro Edition Software expands the ease of use, flexibility, and performance of the standard Platform Designer system design tool. Our training course, System Design with Platform Designer, explores the differences between the Intel Quartus Prime Standard and Pro Edition Software versions of the tools, focusing on Platform Designer support for generic components in the Pro Edition - the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.
The Platform Designer supports new features that greatly help with design portability. You can now:
- Accelerate design creation by using IP presets for Intel and third party boards.
- Allow coherency signals from Intel® Agilex™ and Intel® Stratix® 10 FPGA hard processor system (HPS) interface to be transported to IP via ACE-Lite support.
- Generate hierarchical simulation scripts by referencing simulation information of its subsystems and IP components without traversing system hierarchy.
- Use Verilog syntax to connect ports in the Platform Designer with wire-level connectivity.
- Incorporate IP components that use SystemVerilog interfaces into Platform Designer systems.
- Experience significant reduction in IP upgrade regeneration time
- More details on all these features are available in the Platform Designer User Guide.