Platform Designer

The Platform Designer is the next-generation system integration tool in the Intel® Quartus® Prime Software. The Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. The Platform Designer utilizes a powerful hierarchical framework to offer fast response times for interconnecting large systems, while also providing support for blackbox entities. This enables the Platform Designer to provide fast response times while opening systems and creating new connections by regenerating or operating on IP blocks that have changed. The new Platform Designer tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.

The Platform Designer in the Intel Quartus Prime Pro Edition Software expands the ease of use, flexibility, and performance of the standard Platform Designer system design tool. Our training course, System Design with Platform Designer, explores the differences between the Intel Quartus Prime Standard and Pro Edition Software versions of the tools, focusing on Platform Designer support for generic components in the Pro Edition - the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.

The Platform Designer supports new features that greatly help with design portability. You can now:

  • Accelerate design creation by using IP presets for Intel and third party boards.
  • Allow coherency signals from Intel® Agilex™ and Intel® Stratix® 10 FPGA hard processor system (HPS) interface to be transported to IP via ACE-Lite support.
  • Generate hierarchical simulation scripts by referencing simulation information of its subsystems and IP components without traversing system hierarchy.
  • Use Verilog syntax to connect ports in the Platform Designer with wire-level connectivity.
  • Incorporate IP components that use SystemVerilog interfaces into Platform Designer systems.
  • Experience significant reduction in IP upgrade regeneration time
  • More details on all these features are available in the Platform Designer User Guide.

Platform Designer (Standard / Platform Designer Pro)

Platform Designer (Standard) / Platform Designer Pro Advantages

Board awareness
  • Faster design creation for Intel and 3rd party boards
  • Ability to apply IP presets with pre-assigned pin locations and IO standards for a target board

Faster development
  • Easy-to-use GUI interface enables quick integration between IP functions and subsystems
  • Automatic generation of interconnect logic (address/data bus connections, bus width matching logic, address decoder logic, arbitration logic, etc.)
  • Availability of plug-and-play Platform Designer-compliant IP. (Note: Platform Designer-Pro compliance is not available for all IP)
  • Support mixing of different industry-standard interfaces including Avalon®, Arm AMBA AXI, AMBA APB, and AMBA AHB interfaces
  • Automatic HDL generation of your system
  • Hierarchical design flow enables scalable designs, team-based design, and maximizes design reuse
  • Migration flow to Platform Designer (does not apply to Platform Designer Pro) for SOPC Builder designs

Faster timing closure
  • High-performance Platform Designer (Standard) interconnect based on the NoC architecture and automatic pipelining delivers higher performance compared to SOPC Builder’s system interconnect fabric
  • Ability to control the aggressiveness of automatic pipelining to meet fMAX and latency system requirements

Faster verification
  • Ability to start your simulation faster with automatic testbench generation and by using the verification IP suite
  • Faster board bring-up with System Console by sending read-and-write transactions into a live system
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Demonstrations

Board Awareness in Platform Designer: Board Author Flow

Learn how to use the board awareness feature to create board and IP preset files that include details such as device family, device parts, pin assignments, I/O standards and IP settings for a target board to enable simpler design creation from the get-go.

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Board Awareness in Platform Designer: End User Flow

Learn how to accelerate the design process by using the new board awareness capability in platform designer.

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Design Example Discovery

Learn how to save time in the design process by easily accessing design examples from various repositories, including online design examples from the Intel Design Store and pre-installed design examples that are shipped as part of Quartus.

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AMBA AXI and Avalon Interoperation Using Platform Designer (Standard)

See how seamless it is to integrate IP components with AMBA AXI interfaces with Avalon interfaces using the Platform Designer (Standard).

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Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.