Viterbi Intel® FPGA IP Core

The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders.

Read the Viterbi IP core user guide ›

Viterbi Intel® FPGA IP Core

Viterbi decoding (also known as maximum likelihood decoding or forward dynamic programming) is the most common way of decoding convolutional codes by using an asymptotically optimum decoding technique. In its basic form, Viterbi decoding is an efficient, recursive algorithm that performs an optimal exhaustive search. A convolutional encoder and Viterbi decoder are typically used together to provide error correction over a noisy channel. For example, a communications channel.

Features

Features of the Viterbi Intel FPGA IP core include:

  • High-speed parallel architecture with
  • Performance of over 240 Mbps
  • Fully parallel operation
  • Enhanced block decoding and continuous decoding
  • Low-speed to medium-speed, hybrid architecture
  • Configurable number of add compare and select (ACS) units
  • Memory-based architecture
  • Wide range of performance and logic area
  • Fully parameterized Viterbi decoder, including:
  • Number of coded bits
  • Constraint length
  • Number of soft bits
  • Traceback length
  • Polynomial for each coded bit
  • Variable constraint length
  • Modulation support
  • Trellis coded modulation (TCM) option
  • Simulation and verification
  • VHDL testbenches to verify the decoder
  • Intellectual property (IP) functional simulation models for use in Intel FPGA-supported VHDL and Verilog HDL simulators
  • Interfaces and tools
  • Avalon® streaming interfaces
  • DSP Builder for Intel FPGAs

Additional Resources

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For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

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