Intel® Arria® 10 FPGAs & SoCs

Highest Performance FPGA and SoC at 20 nm1

Intel® Arria® 10 FPGAs deliver more than a speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available OpenCore designs.1 Intel® Arria® 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry’s only hard floating-point digital signal processing (DSP) blocks with speeds up to 1.5 tera floating-point operations per second (TFLOPS).1

The 20 nm ARM*-based Intel® Arria® 10 SoC delivers optimal performance, power efficiency, small form factor, and low cost for midrange applications. The Intel Arria 10 SoC, based on TSMC’s 20 nm process technology, combines a dual-core ARM Cortex*-A9 MPCore* Hard Processor System (HPS) with industry-leading programmable logic technology that includes hardened floating-point digital signal processing (DSP) blocks. The Intel Arria 10 SoC offers a processor with a rich feature set of embedded peripherals, hardened floating-point variable-precision DSP blocks, embedded high-speed transceivers, hard memory controllers, and protocol intellectual property (IP) controllers - all in a single highly integrated package.

See also: Intel® Arria® 10 FPGAs & SoCs Design Software, Design Store, Downloads, Community, and Support

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Intel® Arria® 10 FPGAs & SoCs

Highest Performance 20 nm FPGAs and SoC FPGAs1

Intel® Arria® 10 FPGAs deliver more than a speed grade faster core performance and up to a 20% Fmax advantage compared to the competition, using publicly available OpenCores designs.1 In addition, the Intel® Arria® 10 family offers the programmable logic industry’s only 20 nm ARM*-based SoC FPGAs, delivering clock speeds at up to 1.5 GHz. The Intel® Arria® 10 family also delivers the first hardened support for floating point operations in an FPGA, enabling a new level of DSP performance.

Intel® Arria® 10 SoC FPGAs: When Architecture Matters

Intel® Arria® 10 SoC FPGAs integrate an ARM*-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. It combines the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. The Intel® Arria® 10 SoCs, based on TSMC’s 20 nm process technology, combine a dual-core ARM* Cortex*-A9 MPCore* HPS with industry-leading programmable logic technology that includes hardened floating-point digital signal processing (DSP) blocks.

Hard Processor System (HPS)

Intel® Arria® 10 SoCs feature a second-generation dual-core ARM* Cortex*-A9 MPCore* processor-based hard processor system (HPS) that is faster, more secure, and software compatible with previous-generation SoCs. With Intel® Arria® 10 SoCs you can reduce board size while increasing performance by integrating a GHz-class processor, FPGA logic, and digital signal processing (DSP) functions into a single user-customizable system on a chip. Intel® Arria® 10 SoCs offer the broadest selection of FPGA logic densities to date. These improvements address the performance, power, and security requirements of next-generation communications, broadcast, and computer and storage equipment.

Faster

At 1.5 GHz, the processor provides more than50% increase in performance over the previous generation with 30% power reduction.

More Secure

Intel® Arria® 10 SoCs support secure boot with authentication based on Elliptical Curve Digital Signature Authentication (EC DSA), with a layered public key infrastructure for root of trust support, Advanced Encryption Standard (AES) and new anti-tamper features.

Improved Architecture

Intel® Arria® 10 HPS now has three Ethernet MAC cores, 256 KB Scratch-RAM, supports 8 and 16 bit NAND flash devices, eMMC SD/SDIO/MMC cards, and 72 bit DDR3/4 memory.

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Intel® Arria® 10 SoC Family HPS Features

The HPS is common to all the devices in the Intel® Arria® 10 SoC series.

Processor

Dual-core ARM* Cortex-A9* MPCore* processor with ARM* CoreSight* debug and trace technology.

Coprocessors

Vector floating-point unit (VFPU) single and double precision, ARM* NEON* media processing engine for each processor snoop control unit (SCU), acceleration coherency port (ACP).

Level 1 Cache

32 KB L1 instruction cache, 32 KB L1 data cache.

Level 2 Cache

512 KB shared L2 cache.

Scratch Pad RAM

256 KB.

HPS DDR Memory

DDR4 and DDR3 (up to 64 bit with error correction code (ECC)).

Direct Memory Access (DMA) Controller

8-channel direct memory access (DMA).

Ethernet Media Access Controller (EMAC)

3 x 10/100/1000 EMAC with integrated DMA.

USB On-The-Go Controller (OTG)

2x USB OTG with integrated DMA.

UART Controller

2x UART 16550 compatible.

Serial Peripheral Interface (SPI) Controller

4x SPI.

I2C Controller

5x I2C.

QSPI Flash Controller

1x SIO, DIO, QIO SPI flash supported.

SD/SDIO/MMC Controller

1x eMMC 4.5 with DMA and CE-ATA support.

NAND Flash Controller

1x ONFI 1.0 or later 8 and 16 bit support.

General-purpose I/O (GPIO)

Maximum 62 software-programmable GPIO.

Timers

7X general-purpose timers, 4X watchdog timers.

Security

Secureboot, Advanced Encryption Standard (AES) and authentication based on Elliptic Curve Digital Signature Algorithm (ECDSA).

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Transceivers

High-Bandwidth, Low-Latency Transceivers for Reliable Communication

Intel® Arria® 10 FPGA and SoC serial transceivers offer high bandwidth, low latency, and the lowest power to help you build high-speed communication systems.2 Whether getting data across a board, distributing data to server blades across a backplane, moving data to the next chassis in a data center, or transporting data across the world through a sophisticated optical transport network, the Intel® Arria® 10 FPGA and SoC transceivers provide a wide range of capabilities to support an extensive set of protocols and deliver reliable bandwidth at low cost.

Intel® Arria® 10 FPGA and SoC Transceiver Applications

Intel® Arria® 10 FPGA and SoC transceivers are well suited for:

  • Remote radio heads.
  • Nx100G data transmission.
  • Server acceleration.
  • 4K video processing.
  • Military radar.
  • And many more high-bandwidth applications.
  • Built on 20 nm process technology, the Intel® Arria® 10 FPGAs and SoCs provide over 3.3 Tbps of total serial bandwidth. Intel® Arria® 10 GX devices offer up to 96 channels at 17.4 Gbps for short-reach applications as well as up to 12.5 Gbps for backplane support. In addition, the Intel® Arria® 10 GT FPGAs offers data rates up to 25.78 Gbps bringing high-end bandwidth performance into a midrange device.

Intel® Arria® 10 FPGA and SoC Transceiver Features

The Intel® Arria® 10 FPGA and SoC transceivers have a versatile feature set to handle a wide range of links and provide error-free link operation, including full-featured physical medium attachment (PMA) and hard physical coding sublayer (PCS) layers. In addition, dedicated PCI Express* (PCIe*) hard intellectual property (IP) blocks provide a full hardened protocol stack to support PCIe* Gen1, Gen2, and Gen3x8. The following figure shows the rich set of capabilities that are available to implement high-speed serial links with benefits described.

Features

Chip-to-chip Data Rates

125 Mbps to 17.4 Gbps (Intel® Arria® 10 GX devices).

125 Mbps to 25.78 Gbps (Intel® Arria® 10 GT devices).

Backplane Support

Drive backplanes at data rates up to 12.5 Gbps.

Optical Module Support

SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4.

Cable Driving Support

SFP+ Direct Attach, PCIe* over cable, eSATA.

Transmit Pre-emphasis

5-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss.

Dual-Mode Continuous Time Linear Equalizer (CTLE)

High-gain and high-data rate mode receiver linear equalization to compensate system channel loss.

Decision Feedback Equalizer (DFE)

11-fixed tap DFEs to equalize backplane channel loss in the presence of crosstalk and noisy environments.

Variable Gain Amplifier (VGA)

Broadband amplifier to maximize input dynamic range.

Altera Digital Adaptive Parametric Tuning (ADAPT)

All digital adaptation engine to automatically adjust all link equalization parameters—including CTLE, DFE, and VGA blocks—which provide optimal link margin without intervention from user logic.

Precision Signal Integrity Calibration Engine (PreSICE)

Hardened calibration controller to quickly calibrate all transceiver calibration parameters on power-up for optimal signal integrity performance.

ATX Transmit Phased Locked-Loops (PLLs)

Ultra-low jitter LC (inductor-capacitor) transmit PLLs with continuous tuning range to cover a wide range of standard and proprietary protocols.

Clock Mulitpler PLLs (CMU PLL)

Ring oscillator-based transmit clock sources for multirate applications.

Fractional PLLs (fPLL)

On-chip fractional frequency synthesizers to replace on board crystal oscillators and reduce system cost.

Digitally-Assisted Hybrid Clock-Data Recovery (CDR)

Superior jitter tolerance with fast lock time with independent channel PLL.

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DSP Block Modes

The three DSP block modes available are as follows:

  • Floating-point mode.
  • Standard-precision mode.
  • High-precision mode.

Hardened Floating-Point Processing in Intel® Arria® 10 FPGAs and SoCs

In Intel® Arria® 10 devices, Intel has enhanced the variable-precision DSP block by including hardened floating-point operators. The Intel® Arria® 10 FPGA and SoC variable-precision DSP block introduces a new floating-point mode that delivers breakthrough floating-point performance of up to 1.5 TeraFLOPs.

The architectural innovation in the implementation of IEEE 754 single-precision hardened floating-point DSP (digital signal processing) blocks in Intel® Arria® 10 FPGAs and SoCs enable processing rates up to 1.5 TFLOPs (Tera Floating-point Operations Per Second) and power efficiency up to 40 GFLOPs/Watt.

With the three modes available for Intel® Arria® 10DSP blocks: standard-precision fixed-point, high-precision fixed point and single-precision floating-point, designers can implement a variety of algorithms that require fixed point all the way to double-precision IEEE 754 compliant floating-point operations. Hardened floating-point processing offers designers the ability to implement algorithms in floating point with the similar performance and power efficiency as fixed point. This can be achieved without any power, area, or density compromises and with no loss of fixed-point features or functionality.

Intel® Arria® 10 FPGAs and SoCs are a compelling solution for industrial, wireless systems, compute intensive applications such as high-performance computing, machine learning, high-precision radars and data center acceleration applications.

Floating-Point Mode

A single DSP block in the floating-point mode provides an IEEE 754 single-precision floating-point multiplier and an IEEE 754 single-precision adder, delivering the highest floating-point performance on any FPGA in the market. These floating-point operators allow floating-point designs to be similar to traditional fixed-point designs, providing the benefits of floating-point at no additional cost for FPGA designers. Also, designers are able to remain in floating point, eliminating months of converting algorithms to fixed point and verifying the accuracy.

The floating-point mode offers:

  • An IEEE 754 single-precision multiplier and IEEE 754 single-precision adder in each DSP block.
  • Support for floating-point operations, such as: AxB, A+C, A-C, AxB+C, AxB-C, Acc=AxB+Acc.
  • Vector operations to support convolution, dot products, and other linear algebra functions.
  • Complex multiplication using fast Fourier transform (FFT).

In addition to floating-point capabilities, the new variable prevision block includes:

  • Internal pipeline registers for faster fMAX and lower power consumption.
  • 108 inputs, 74 outputs.
  • 18x19 multiply mode, allowing the pre-adder to use two 18 bit inputs.
  • Optional second accumulator (feedback register) for complex serial filtering.
  • Dual 18x19 independent multipliers.
  • Built-in 18 bit or 28 bit coefficient register banks, available with or without the pre-adder function.

Cascade Bus

All DSP block modes feature a 64 bit accumulator and each variable-precision DSP block comes with a 64 bit cascade bus. The cascade bus allows the implementation of even higher precision signal processing through cascading multiple blocks using a dedicated bus.

The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18 bit DSP applications, such as high-definition video processing, digital up-or down-conversion and multirate filtering.

A complete suite of tools to accelerate designer’s productivity include model-based, C-based, and HDL/IP-based design entry.

Need even more floating-point performance? Intel® Arria® 10 designs offer a seamless design and device migration path to Stratix 10 devices offering up to 10 TFLOPS of performance. For more information, contact your local sales representative.

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Product and Performance Information

1

Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

2

Intel® technologies' features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at http://www.intel.com.