2.1. Device Footprint
2.2. Power Management
2.3. Configuration
2.4. Design Security Differences
2.5. Logic Elements and Embedded Memory
2.6. PLL and Clock Network
2.7. Digital Signal Processing (DSP)
2.8. I/O Interfaces
2.9. LVDS SERDES Interface
2.10. Sensor Monitoring System
2.11. MIPI D-PHY Interface
2.12. External Memory Interface (EMIF)
2.13. Hard Processor System (HPS)
2.14. Transceiver and Serial Protocols
2.15. PCIe Interface
2.16. Ethernet Interface
2.3.1. General Configuration Pin and Sequences
2.3.2. Device Configuration and the Secure Device Manager (SDM)
2.3.3. Active Serial (AS) Configuration
2.3.4. Avalon® -ST Configuration
2.3.5. JTAG Configuration
2.3.6. Configuration via Protocol (CvP)
2.3.7. QSPI Flash Access and Remote System Upgrade Feature
2.3.8. SEU Features
2.3.9. Configuration File Format Differences
2.14.4. Transceiver Reset
Agilex™ 3 device uses the embedded soft reset controller inside the transceivers that is very similar to the embedded reset controller for the Cyclone® V device. Due to the architectural differences and some specific reset operations between the devices, reset controller migration from the Cyclone® V to Agilex™ 3 device is not possible.
The following table highlights the key differences in the transceiver reset between Cyclone® V and Agilex™ 3 devices:
| Feature | Cyclone® V | Agilex™ 3 |
|---|---|---|
| Architecture | Transceiver reset operation using only embedded reset controller. | Transceiver reset operation using embedded soft reset controller, and requires reset sequencing. |
The key difference is Agilex™ 3 reset operation requires reset sequencing for each transceiver channel to operate correctly. Thus, there is a new GTS Reset Sequencer Intel FPGA IP in the Agilex™ 3 device to handle the necessary sequencing. For more information about the GTS Reset Sequencer IP Intel FPGA IP and the reset sequencing, refer to the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs.