Cyclone® V to Agilex™ 3 Device Migration Guide

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ID 857720
Date 7/08/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Quartus Prime and Platform Designer Migration Guidelines A. Document Revision History for Cyclone® V to Agilex™ 3 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 3 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
1. Overview
2. Device Migration Considerations
3. Quartus Prime and Platform Designer Migration Guidelines
A. Document Revision History for Cyclone® V to Agilex™ 3 Device Migration Guide

2.8.4. HVIO Bank

The guidelines in this topic apply when switching your FPGA and board design from a Cyclone® V device to Agilex™ 3 device.

Cyclone® V device supports a wider VCCIO range, while Agilex™ 3 HVIO bank targets a higher VCCIO supply range. For lower voltage range, refer to the "HSIO Banks" section in the General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs.

Each HVIO block contains two HVIO banks. Each HVIO bank is further divided into 20 I/O pins per bank, and each HVIO block has its individual fabric-feeding I/O PLL.

The following table lists the I/O standard and features comparison between Cyclone® V and Agilex™ 3 devices:

Table 19.  I/O Types and Standards Comparison
I/O Types Cyclone® V I/O Standards Agilex™ 3 HVIO I/O Standards
Single-ended non-voltage referenced
  • 3.3 V LVTTL/3.3 V LVCMOS
  • 3.0 V LVTTL/3.0 V LVCMOS
  • 3.0 V PCI
  • 3.0 V PCI-X
  • 2.5 V LVCMOS
  • 1.8 V LVCMOS
  • 1.5 V LVCMOS
  • 1.2 V LVCMOS
  • 1.8 V LVCMOS/LVTTL
  • 2.5 V LVCMOS/LVTTL
  • 3.3 V LVCMOS/LVTTL
Single-ended and pseudo-differential voltage-referenced
  • SSTL-2
  • SSTL-18
  • SSTL-15
  • HSUL-12
  • 1.8 V HSTL
  • 1.5 V HSTL
  • 1.2 V HSTL

–

Note: Single-ended and pseudo-differential voltage-referenced are supported with HSIO. Refer to HSIO Bank for more information.
True differential
  • LVDS
  • RSDS
  • Mini-LVDS
  • LVPECL
  • SLVS
  • Sub-LVDS
  • HiSPi

–

Note: True Differential is supported with HSIO. Refer to HSIO Bank for more information.
Table 20.  I/O Features Comparison
Feature Cyclone® V Agilex™ 3 HVIO
Programmable slew rate Yes No
Programmable output buffer delay Yes Yes
Programmable bus hold Yes No
Programmable weak pull-up resistor Yes, 25K ohms Yes, 20K ohms
Programmable weak pull-down resistor No Yes, 20K ohms
On-chip clamp diode Yes No
Programmable current strength Yes, 2, 4, 6, 8, 10, 12 mA Yes, 3, 6, 9, 12 mA
OCT termination Yes No
Dynamic OCT Yes No
Output enable Yes Yes

Apart from the available features, there are dual-purpose pins to accommodate the usage of the transceiver and Reduced Gigabit Media Independent Interface (RGMII) for each I/O pin in the HVIO bank.

Due to the architectural differences between Cyclone® V and Agilex™ 3 devices, the I/O design guidelines differ for these devices. You must replan your FPGA pin and resource sharing when switching from Cyclone® V FPGA I/O to Agilex™ 3 HVIO bank. Refer to the Agilex™ 3 FPGAs and SoCs Device Data Sheet, General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs, and GTS Transceiver PHY User Guide for more information.

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