2.1. Device Footprint
2.2. Power Management
2.3. Configuration
2.4. Design Security Differences
2.5. Logic Elements and Embedded Memory
2.6. PLL and Clock Network
2.7. Digital Signal Processing (DSP)
2.8. I/O Interfaces
2.9. LVDS SERDES Interface
2.10. Sensor Monitoring System
2.11. MIPI D-PHY Interface
2.12. External Memory Interface (EMIF)
2.13. Hard Processor System (HPS)
2.14. Transceiver and Serial Protocols
2.15. PCIe Interface
2.16. Ethernet Interface
2.3.1. General Configuration Pin and Sequences
2.3.2. Device Configuration and the Secure Device Manager (SDM)
2.3.3. Active Serial (AS) Configuration
2.3.4. Avalon® -ST Configuration
2.3.5. JTAG Configuration
2.3.6. Configuration via Protocol (CvP)
2.3.7. QSPI Flash Access and Remote System Upgrade Feature
2.3.8. SEU Features
2.3.9. Configuration File Format Differences
2.14. Transceiver and Serial Protocols
Agilex™ 3 devices significantly uplift the transceiver capability and performance from Cyclone® V devices. Hence, you cannot directly migrate existing Cyclone® V transceiver designs to Agilex™ 3 devices.
The following table outlines the key differences and their associated guidance that you must be aware of when upgrading to use Agilex™ 3 GTS transceivers:
| Key Differences | Cyclone® V Transceivers | Agilex™ 3 GTS Transceivers | Guidance for upgrading to Agilex™ 3 GTS Transceivers |
|---|---|---|---|
| Hardened block resources | PCS (8b/10b-based) | PCS (64b/66b-based), FEC (Firecode, Reed-Solomon), and 10G Ethernet HIP |
Create user-logic if 8b/10b-based PCS is required or use Intel protocol IPs that include solutions for 8b/10b-PCS (for example, Triple-Speed Ethernet for Intel FPGA IP). |
| Channel placement considerations | Based on hard IP (PCIe) availability and clocking resources (transmit PLL and clock line). | Based on hard IP (PCIe, Ethernet) availability and bonded configuration. | For bonded configuration in Agilex™ 3, follow the Bonding Placement Requirements in GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs for the correct channel placement. |
| Clocking flexibility | Channels must share either CMU, fPLL, or channel PLL with consideration of clock-line availability. | Each channel has its own TX PLL. One system PLL is available per bank. |
No TX PLL sharing required across the channels. If multiple channels use the same rate, each channel is driven by its own TX PLL sharing the same REFCLK source. |
| Reference for calibration circuit | Via RREF pair to external resistor | Via RCOMP pair to external resistor. | Identify the external resistor value differences. |
The differences listed in the above table are not exhaustive and are meant to highlight specific Cyclone® V transceiver features that are different in Agilex™ 3 GTS transceiver. For detailed information about the new features enabled in Agilex™ 3 GTS transceiver, refer to the GTS Transceiver PHY User Guide .