3. Quartus Prime and Platform Designer Migration Guidelines

Cyclone® V to Agilex™ 3 Device Migration Guide

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ID 857720

Date 7/08/2025

Version current

Public

Document Table of Contents

Document Table of Contents x

1. Overview 2. Device Migration Considerations 3. Quartus Prime and Platform Designer Migration Guidelines A. Document Revision History for Cyclone® V to Agilex™ 3 Device Migration Guide

2. Device Migration Considerations x

2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface

2.3. Configuration x

2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences

2.8. I/O Interfaces x

2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank

2.13. Hard Processor System (HPS) x

2.13.1. HPS Boot Flows

2.14. Transceiver and Serial Protocols x

2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset

3. Quartus Prime and Platform Designer Migration Guidelines x

3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 3 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance

3.3. Upgrading IP Cores and Platform Designer Systems x

3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device

1. Overview

2. Device Migration Considerations

2.1. Device Footprint

2.2. Power Management

2.3. Configuration

2.3.1. General Configuration Pin and Sequences

2.3.2. Device Configuration and the Secure Device Manager (SDM)

2.3.3. Active Serial (AS) Configuration

2.3.4. Avalon® -ST Configuration

2.3.5. JTAG Configuration

2.3.6. Configuration via Protocol (CvP)

2.3.7. QSPI Flash Access and Remote System Upgrade Feature

2.3.8. SEU Features

2.3.9. Configuration File Format Differences

2.4. Design Security Differences

2.5. Logic Elements and Embedded Memory

2.6. PLL and Clock Network

2.7. Digital Signal Processing (DSP)

2.8. I/O Interfaces

2.8.1. HSIO Bank

2.8.2. HPS I/O Bank

2.8.3. SDM I/O Bank

2.8.4. HVIO Bank

2.9. LVDS SERDES Interface

2.10. Sensor Monitoring System

2.11. MIPI D-PHY Interface

2.12. External Memory Interface (EMIF)

2.13. Hard Processor System (HPS)

2.13.1. HPS Boot Flows

2.14. Transceiver and Serial Protocols

2.14.1. PMA Architecture

2.14.2. PCS Architecture

2.14.3. Transceiver Clocking

2.14.4. Transceiver Reset

2.15. PCIe Interface

2.16. Ethernet Interface

3. Quartus Prime and Platform Designer Migration Guidelines

3.1. Overview

3.2. IP Comparison Between Cyclone® V and Agilex™ 3 Devices

3.3. Upgrading IP Cores and Platform Designer Systems

3.3.1. Upgrading IP Cores via Quartus® Prime Software Project

3.3.2. Upgrading IP Cores in Platform Designer

3.3.3. Migrating IP Cores to a Different Device

3.4. RTL Compliance

A. Document Revision History for Cyclone® V to Agilex™ 3 Device Migration Guide