AN 1020: Using the FPGA AI Suite IP with High Bandwidth Memory on Stratix® 10 MX and Agilex™ 7 M-Series Devices
2.2. HBM Connection Considerations
The HBM memory controller exposes 32 AXI4 pseudo channels for both stacks of HBM (that is, 16 pseudo channels with 256-bit data width for each stack). The 16 pseudo channels for a stack address 8 channels of 2 GB address space each per layer in the stack. This configuration allows for a very large bandwidth. However, the current implementation of the FPGA AI Suite IP, with only one AXI4 channel per IP, limits how much of the available bandwidth can be used by the FPGA AI Suite IP instances.
To take advantage of HBM with the FPGA AI Suite IP, consider the following aspects of your FPGA AI Suite IP memory requirements: