AN 1020: Using the FPGA AI Suite IP with High Bandwidth Memory on Stratix® 10 MX and Agilex™ 7 M-Series Devices
2.1. Current FPGA AI Suite IP Implementation With DDR4
The FPGA AI Suite IP, in its current implementation, has a 512-bit wide data and a 32-bit wide address bus and therefore can address a maximum of 4GB of external memory. The current FPGA AI Suite design examples all assume that the required memory is external on the PCB, either soldered on the PCB or as DDR4 modules in PCB DIMM slots.
The following figure shows an example of a system with four FPGA AI Suite IP instances connected to four external DDR memories with four separate AXI4 buses.
Figure 4. System with Four FPGA AI Suite IP Instances Connected to Four External DDR Memories