Agilex™ 7 M-Series Known Issue List

ID 851750
Date 4/18/2025
Public
Document Table of Contents

2.2.9. LPDDR5 and DDR5 controller does not support non-aligned transactions

Description

In LPDDR5 and DDR5 memory interfaces, when using x16 configuration in any access mode, data corruption occurs when non-aligned transactions are issued to the controller.

Impacted configurations:

  • LPDDR5 x16 1-channel
  • DDR5 x16 1-channel
  • LPDDR5 x16 2-channel
  • DDR5 x16 2-channel
Note: LPDDR5 x16 2-channel and DDR5 x16 2-channel with HPS are not supported in Agilex™ 7 M-Series devices.

Workaround

We recommend using aligned transactions.

Status

Table 35.  Device Status Table
Devices Affected Planned Fix
  • AGMx0xxR47Axxxx
  • AGMx0xxR31Bxxxx
None