Agilex™ 7 M-Series Known Issue List

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ID 851750
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Known Issue List for Devices 3. Arm* Cortex*-A53 MPCore and CoreSight* Errata 4. Agilex™ 7 M-Series User Guidelines 5. Document Revision History for the Agilex™ 7 M-Series Known Issue List
2. Known Issue List for Devices x
2.1. FPGA 2.2. EMIF 2.3. Configuration and Security 2.4. Fabric NoC 2.5. Device Power Supply, Core, I/O 2.6. HPS
2.1. FPGA x
2.1.1. F-Tile 2.1.2. R-Tile
2.1.1. F-Tile x
2.1.1.1. Requirement for F-Tile Devices which are Powered and Unconfigured 2.1.1.2. FGT PAM4 Compliance Support 2.1.1.3. FGT Transceivers Do Not Support Direct EXTEST JTAG Instruction in Boundary Scan Test 2.1.1.4. F-Tile: Unsuccessful TX Equalization Description Workaround Status 2.1.1.5. Link May Not Downgrade With Corrupt Lanes (F-Tile) 2.1.1.6. Occasional Equalization Timeout or PCIe Link Training Failure to Achieve Expected Link Speed during Link Disable, Hot Reset, and Speed Change 2.1.1.7. Link Fault Detection window of the F-Tile Ethernet Hard IP in 10GE-1 or 25GE-1 mode 2.1.1.8. FHT PMA Transmitter-to-Receiver Internal Serial Loopback operation for error-free BER results 2.1.1.9. F-Tile Ethernet Hard IP rst_tx_stats and rst_rx_stats register bits might not function correctly 2.1.1.10. F-Tile Ethernet Hard IP force_rf register bit might not function correctly 2.1.1.11. F-Tile Ethernet Hard IP tx_pause_request register bit might not function correctly 2.1.1.12. F-Tile Ethernet Hard IP PTP statistics might not clear correctly 2.1.1.13. F-Tile Ethernet Hard IP unable to achieve 100% throughput with some variants 2.1.1.14. F-Tile 400G Ethernet IP RX Priority Flow Control Issue 2.1.1.15. F-Tile Ethernet Hard IP Bidirectional Link Fault Signaling Issue 2.1.1.16. F-Tile SDI II IP and F-Tile PMA/FEC Direct PHY IP with “SDI” configuration rule are not of production quality 2.1.1.17. F-Tile HDMI IP and F-Tile PMA/FEC Direct PHY IP with 'HDMI' configuration rule are not of production quality 2.1.1.18. Ethernet Auto-Negotiation and Link Training (AN/LT) designs on F-Tile FGT may not link up when using Quartus Prime Pro Edition software version 25.1.1 and 25.3 2.1.1.19. IEEE 802.3-2022 50GBASE-KR compliance testing instability during Link Training (LT)
2.1.2. R-Tile x
2.1.2.1. Gen3/Gen4 link might be established without successfully performing Transmit Equalization (TX EQ) 2.1.2.2. Link may not downgrade with corrupt lanes 2.1.2.3. Malformed TLP incorrectly flagged as ECRC error 2.1.2.4. Assertion of PERST / warm reset during the Functional Level Reset results in PCIe* Link Failure 2.1.2.5. No Support for Page Request Services in Port 2 and Port 3 of 4x4 Configuration 2.1.2.6. Multiple Fatal Error Messages 2.1.2.7. PCIe* x4 cores may report Uncorrectable Fatal Error or Malformed TLP 2.1.2.8. Receiver Errors logged during back-to-back Secondary Bus Resets (SBR) operations when running at Gen 2 speed 2.1.2.9. Polling.Active time out during Link Disable-Enable loop tests 2.1.2.10. CXL 1.1 version does not support uncorrectable error reporting when receiving two LLCTRL-Init packet 2.1.2.11. R-tile might report Fatal Error in the Advance Error Reporting (AER) registers when using Address Translation Service (ATS)
2.2. EMIF x
2.2.1. DDR5 x32 + user bits through NoC is not supported 2.2.2. PhyMux EMIF lockstep pinout configurations Restrictions 2.2.3. GPIO-B blocked in mixed GPIO-B/EMIF use cases 2.2.4. DDR4 rDBI is not working 2.2.5. LPDDR5 and DDR5 reduced sequential write/read bandwidth when using Fabric Sync Fabric direct mode in x16 2-channel configuration 2.2.6. LPDDR5 and DDR5 maximum bandwidth for sequential short write is limited 2.2.7. LPDDR5 and DDR5 controller does not support non-aligned transactions
2.3. Configuration and Security x
2.3.1. AS Fast mode BootROM delay
2.4. Fabric NoC x
2.4.1. Lower than expected performance with Fabric NoC-enabled design
2.5. Device Power Supply, Core, I/O x
2.5.1. I/O PLL reference clock frequency and duty cycle specification update
2.6. HPS x
2.6.1. HPS EMAC RX Interface In Unresponsive State
3. Arm* Cortex*-A53 MPCore and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction Might Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
4. Agilex™ 7 M-Series User Guidelines x
4.1. Power Estimation Guardband
1. About This Document
2. Known Issue List for Devices
3. Arm* Cortex*-A53 MPCore and CoreSight* Errata
4. Agilex™ 7 M-Series User Guidelines
5. Document Revision History for the Agilex™ 7 M-Series Known Issue List

2.1.1.4. F-Tile: Unsuccessful TX Equalization

Description

In the F-Tile IP for PCIe* , when a speed change to Gen3/Gen4 speed is attempted for the first time with full TxEq enabled, if all phases of equalization do not successfully complete, the link reverts back to the lowest speed that passed equalization. The Equalization results for Gen3 and Gen4 are recorded in the following registers:
  • For Gen3: Link Status 2 Register [4:1]:
    • [1] Equalization 8.0 GT/s Complete
    • [2] Equalization 8.0 GT/s Phase 1 Successful
    • [3] Equalization 8.0 GT/s Phase 2 Successful
    • [4] Equalization 8.0 GT/s Phase 3 Successful
    ​
  • For Gen4: 16.0 GT/s Status Register [3:0]​
    • [0] Equalization 16.0 GT/s Complete
    • [1] Equalization 16.0 GT/s Phase 1 Successful
    • [2] Equalization 16.0 GT/s Phase 2 Successful
    • [3] Equalization 16.0 GT/s Phase 3 Successful

If equalization is attempted, the “Complete” bit is set for that speed regardless if the other phases of equalization completed successfully. Once the “Complete” bit is set, the F-Tile permits a speed change by setting the Target Link Speed in the Link Control 2 Register. As a result, the link may train to Gen3/Gen4 speeds with sub-optimal transmitter equalization settings.​

To confirm if the transmitter equalization procedure completed successfully, use software to read the following registers and ensure that all bits are set:
  • For Gen3: Link Status 2 Register [4:1]
  • For Gen4: 16.0 GT/s Status Register [3:0]

To re-initiate the equalization procedure, write 1b to the Perform Equalization bit [0] in the Link Control 3 register.

Workaround

Use software to check that the link equalization procedure was successfully performed:
  • For Gen3: Both Equalization 8.0 GT/s Phase 3 Successful bit and Equalization 8.0 GT/s Complete bit of the Link Status 2 register are set to 1b.
  • For Gen4: Both Equalization 16.0 GT/s Phase 3 Successful bit and Equalization 16.0 GT/s Complete bit of 16.0 GT/s Status Register are set to 1b.
If required, re-initiate the link equalization procedure by:
  1. Writing 1b to the Perform Equalization bit in the Link Control 3 register.
  2. Followed by a write to the Target Link Speed field in the Link Control 2 register to enable the Link to run at 8.0 GT/s or higher.
  3. Followed by a write of 1b to the Retrain Link bit in the Link Control register of the Downstream Port.

Status

Table 6.  Device Status Table
Devices Affected Planned Fix
  • AGMx0xxR47Axxxx
  • AGMx0xxR31Bxxxx
  • AGMx0xxR47Bxxxx
 None
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