Hard Processor System Component Reference Manual: Agilex™ 3 SoCs

ID 851703
Date 5/30/2025
Public
Document Table of Contents

3.5. HPS-to-FPGA AXI* Manager Interface

The HPS-to-FPGA AXI* subordinate interface, hps2fpga, is connected to a AXI* Manager BFM for simulation. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to hps2fpga_axi_clock clock and the reset input is connected to hps2fpga_axi_reset.

Table 22.  Configuration of HPS-to-FPGA AXI* Subordinate BFM
Parameter Value
AXI* Address Width 20-40
AXI* Read Data Width 32, 64 or 128
AXI* Write Data Width 32, 64 or 128
AXI* ID Width 4