Nios® V Processor: Lockstep Implementation User Guide

ID 833274
Date 4/17/2025
Public
Document Table of Contents

2.5.4. Reset LOGS

The LOGS information can be reset in the following ways:

  • Hard asynchronous reset . The whole fRSmartComp is reset along with Host CPU and Agent CPU.
  • Synchronous reset through the following interfaces:
    Interface Actions
    Configuration Interface Writes the ERRCTRL_PGOLOGRST register with 1’b1

The ERRCTRL_PGOLOGRST register is protected with a Key, and after setting a bit to 1’b1, it is necessary to write it back to 1’b0 to remove the reset action.

Table 19.  Synchronous Reset

Bit Field

(ERRCTRL_

PGOLOGRST)
Reset Target
ALARMS CONTEXT STATISTICS
[9:6] - Reserved N/A N/A N/A
[5] – Error Controller - -
  • ERRCTRL_FNGISTAT4 register
[4] – Error Controller
  • ALARM16
  • ALARM17
  • ALARM18
  • ALARM19
  • ERRCTRL_FNGICTXT4 register

-
[3:2] - Reserved N/A N/A N/A
[1] – DCLSM - -
  • ERRCTRL_FNGISTAT0 register
[0] – DCLSM
  • ALARM0
  • ALARM1
  • ALARM2
  • ALARM3
  • ALARM4
  • ERRCTRL_FNGICMPCTXT* registers
-