Nios® V Processor: Lockstep Implementation User Guide

ID 833274
Date 4/17/2025
Public
Document Table of Contents

6.2.1.2.2. Extended Reset Control

The Host CPU, fRSmartComp, and Agent CPU all share the same reset input signal. This allows you to implement dedicated Power-On Reset and Warm reset for each module. You can implement all reset scenarios to enhance system availability.
For more information about reset scenarios, refer to Resetting the CPU upon Fault Detection.
Table 65.  Resets for Every Module in Extended Reset Control
Module Reset
Host CPU

These reset signals affect Host CPU only. Refer to the Nios V Processor Reference Manual on the subchapter Reset and Debug Signals for more information.

  • Host CPU hard asynchronous reset (reset)
  • Host CPU reset request (cpu_resetreq_resetreq)
  • Host CPU reset request acknowledgement (cpu_resetreq_ack)
Agent CPU

These reset signals affect Agent CPU only. Refer to the Nios V Processor Reference Manual on the subchapter Reset and Debug Signals for more information..

  • Agent CPU hard asynchronous reset (reset_r)
  • Agent CPU reset request (reset_req_r)
  • Agent CPU reset request acknowledge (reset_req_ack_r)
fRSmartComp

This reset affects fRSmartComp only. Refer to Extended Reset Interfaces.

  • fRSmartComp hard asynchronous reset (ARSTn)
Figure 22. Example of Simple Extended Reset ControlThis figure assumes all modules shares the same Power-On Reset source from a reset pushbutton on FPGA, and fRSmartComp is the only Warm Reset source.
Note: Since the ALARMS are sticky, the System Supervisor must clear the ALARMS in LOGS information to stop an endless CPU reset requests.