1. About the Nios® V Processor Lockstep
2. Overview
3. Controlling the Nios® V Processor Lockstep
4. Programming Model
5. Signals, Interfaces, and Build Parameters
6. Using Nios® V Processor Lock Step
A. Document Revision History for the Nios® V Processor: Lockstep Implementation User Guide
B. Appendix
4.4.1. CPUs’ Reset Control Register - DCLSM_CPURC
4.4.2. DCLSM Basic Control Register - DCLSM_CTRL
4.4.3. DCLSM Blind Window Control Register - DCLSM_BWCR
4.4.4. All Alarms’ Prior Alarms’ Fault Injection Register - ERRCTRL_ALL_ALARMS_PRIOR_AFI
4.4.5. INTREQ Configuration Register - ERRCTRL_INTREQ_CONF
4.4.6. Timeout Deadline and Status Register - ERRCTRL_TIMEOUT
4.4.7. Timeout Acknowledgment Register - ERRCTRL_TIMEOUT_ACK
4.4.8. Enable Key fRSmartComp Control Register - ERRCTRL_ENABLE_KEY
4.4.9. Root Fault Injection Control register - ERRCTRL_ROOT_INJ
4.4.10. Alarm Fault Injection Control register - ERRCTRL_ALARM_INJ
4.4.11. Event Mask Configuration register - ERRCTRL_MASKA and ERRCTRL_MASKB
4.4.12. Alarm Routing Configuration register - ERRCTRL_ROUTA and ERRCTRL_ROUTB
4.4.13. Error Controller PGO LOG Reset Control register - ERRCTRL_PGOLOGRST
4.4.14. PGO0 and PGO4 Configuration registers - ERRCTRL_PGO0 and ERRCTRL_PGO4
4.4.15. FN_MODEIN Control Register - ERRCTRL_FNMODEIN
4.4.16. FN_MODEOUT register - ERRCTRL_FNMODEOUT
4.4.17. All Alarms After Fault Injection - ERRCTRL_FNGIALARMS
4.4.18. Error Controller Context Register - ERRCTRL_FNGICTXT4
4.4.19. CMP Mismatch CONTEXT Registers - ERRCTRL_FNGICMPCTXT0 … ERRCTRL_FNGICMPCTXT3
4.4.20. STATISTICS registers: ERRCTRL_FNGISTAT0 and ERRCTRL_FNGISTAT4
4.4.21. State register - ERRCTRL_FNPERIPHGI4
6.2.1.2.2. Extended Reset Control
The Host CPU, fRSmartComp, and Agent CPU all share the same reset input signal. This allows you to implement dedicated Power-On Reset and Warm reset for each module. You can implement all reset scenarios to enhance system availability.
For more information about reset scenarios, refer to Resetting the CPU upon Fault Detection.
Module | Reset |
---|---|
Host CPU | These reset signals affect Host CPU only. Refer to the Nios V Processor Reference Manual on the subchapter Reset and Debug Signals for more information.
|
Agent CPU | These reset signals affect Agent CPU only. Refer to the Nios V Processor Reference Manual on the subchapter Reset and Debug Signals for more information..
|
fRSmartComp | This reset affects fRSmartComp only. Refer to Extended Reset Interfaces.
|
Figure 22. Example of Simple Extended Reset ControlThis figure assumes all modules shares the same Power-On Reset source from a reset pushbutton on FPGA, and fRSmartComp is the only Warm Reset source.
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