1. About the Nios® V Processor Lockstep
2. Overview
3. Controlling the Nios® V Processor Lockstep
4. Programming Model
5. Signals, Interfaces, and Build Parameters
6. Using Nios® V Processor Lock Step
A. Document Revision History for the Nios® V Processor: Lockstep Implementation User Guide
B. Appendix
4.4.1. CPUs’ Reset Control Register - DCLSM_CPURC
4.4.2. DCLSM Basic Control Register - DCLSM_CTRL
4.4.3. DCLSM Blind Window Control Register - DCLSM_BWCR
4.4.4. All Alarms’ Prior Alarms’ Fault Injection Register - ERRCTRL_ALL_ALARMS_PRIOR_AFI
4.4.5. INTREQ Configuration Register - ERRCTRL_INTREQ_CONF
4.4.6. Timeout Deadline and Status Register - ERRCTRL_TIMEOUT
4.4.7. Timeout Acknowledgment Register - ERRCTRL_TIMEOUT_ACK
4.4.8. Enable Key fRSmartComp Control Register - ERRCTRL_ENABLE_KEY
4.4.9. Root Fault Injection Control register - ERRCTRL_ROOT_INJ
4.4.10. Alarm Fault Injection Control register - ERRCTRL_ALARM_INJ
4.4.11. Event Mask Configuration register - ERRCTRL_MASKA and ERRCTRL_MASKB
4.4.12. Alarm Routing Configuration register - ERRCTRL_ROUTA and ERRCTRL_ROUTB
4.4.13. Error Controller PGO LOG Reset Control register - ERRCTRL_PGOLOGRST
4.4.14. PGO0 and PGO4 Configuration registers - ERRCTRL_PGO0 and ERRCTRL_PGO4
4.4.15. FN_MODEIN Control Register - ERRCTRL_FNMODEIN
4.4.16. FN_MODEOUT register - ERRCTRL_FNMODEOUT
4.4.17. All Alarms After Fault Injection - ERRCTRL_FNGIALARMS
4.4.18. Error Controller Context Register - ERRCTRL_FNGICTXT4
4.4.19. CMP Mismatch CONTEXT Registers - ERRCTRL_FNGICMPCTXT0 … ERRCTRL_FNGICMPCTXT3
4.4.20. STATISTICS registers: ERRCTRL_FNGISTAT0 and ERRCTRL_FNGISTAT4
4.4.21. State register - ERRCTRL_FNPERIPHGI4
6.2.1.2.1. Basic Reset Control
The Host CPU, fRSmartComp, and Agent CPU all share the same reset input signal from the Power-On Reset. Upon Power-On Reset, the Host CPU and the fRSmartComp are asynchronously reset at the same time, while Agent CPU is asynchronously reset a few clock cycles later to consider Time Diversity.
The basic reset control supports Power-On Reset only; thus you can implement RS_1 and RS_2 only as the Lockstep system’s reset mechanism. Refer to Resetting CPU upon Fault Detection for more information about reset scenarios.
Module | Reset |
---|---|
Host CPU | The reset is similar to a Nios® V processor system without the Lock Step feature (without the fRSmartComp and the Agent CPU). For more information about Host CPU, refer to the Nios® VProcessor Reference Manual: Reset and Debug Signals. |
Agent CPU | The fRSmartComp includes dedicated facilities to generate reset request signal for Agent CPU, based on the Host CPU. The generation is automatic and considers Time Diversity. |
fRSmartComp | The fRSmartComp hard asynchronous reset is connected to the Host CPU reset internally. |
Figure 21. Example of Simple Basic Reset ControlThis figure assumes there is only a single Power-On Reset source from a reset pushbutton on the FPGA.