Nios® V Processor: Lockstep Implementation User Guide

ID 833274
Date 4/17/2025
Public
Document Table of Contents

6.2.1.2.1. Basic Reset Control

The Host CPU, fRSmartComp, and Agent CPU all share the same reset input signal from the Power-On Reset. Upon Power-On Reset, the Host CPU and the fRSmartComp are asynchronously reset at the same time, while Agent CPU is asynchronously reset a few clock cycles later to consider Time Diversity.

The basic reset control supports Power-On Reset only; thus you can implement RS_1 and RS_2 only as the Lockstep system’s reset mechanism. Refer to Resetting CPU upon Fault Detection for more information about reset scenarios.

Module Reset
Host CPU

The reset is similar to a Nios® V processor system without the Lock Step feature (without the fRSmartComp and the Agent CPU).

For more information about Host CPU, refer to the Nios® VProcessor Reference Manual: Reset and Debug Signals.

Agent CPU

The fRSmartComp includes dedicated facilities to generate reset request signal for Agent CPU, based on the Host CPU. The generation is automatic and considers Time Diversity.

fRSmartComp

The fRSmartComp hard asynchronous reset is connected to the Host CPU reset internally.

Figure 21. Example of Simple Basic Reset ControlThis figure assumes there is only a single Power-On Reset source from a reset pushbutton on the FPGA.