1. About the Nios® V Processor Lockstep
2. Overview
3. Controlling the Nios® V Processor Lockstep
4. Programming Model
5. Signals, Interfaces, and Build Parameters
6. Using Nios® V Processor Lock Step
A. Document Revision History for the Nios® V Processor: Lockstep Implementation User Guide
B. Appendix
4.4.1. CPUs’ Reset Control Register - DCLSM_CPURC
4.4.2. DCLSM Basic Control Register - DCLSM_CTRL
4.4.3. DCLSM Blind Window Control Register - DCLSM_BWCR
4.4.4. All Alarms’ Prior Alarms’ Fault Injection Register - ERRCTRL_ALL_ALARMS_PRIOR_AFI
4.4.5. INTREQ Configuration Register - ERRCTRL_INTREQ_CONF
4.4.6. Timeout Deadline and Status Register - ERRCTRL_TIMEOUT
4.4.7. Timeout Acknowledgment Register - ERRCTRL_TIMEOUT_ACK
4.4.8. Enable Key fRSmartComp Control Register - ERRCTRL_ENABLE_KEY
4.4.9. Root Fault Injection Control register - ERRCTRL_ROOT_INJ
4.4.10. Alarm Fault Injection Control register - ERRCTRL_ALARM_INJ
4.4.11. Event Mask Configuration register - ERRCTRL_MASKA and ERRCTRL_MASKB
4.4.12. Alarm Routing Configuration register - ERRCTRL_ROUTA and ERRCTRL_ROUTB
4.4.13. Error Controller PGO LOG Reset Control register - ERRCTRL_PGOLOGRST
4.4.14. PGO0 and PGO4 Configuration registers - ERRCTRL_PGO0 and ERRCTRL_PGO4
4.4.15. FN_MODEIN Control Register - ERRCTRL_FNMODEIN
4.4.16. FN_MODEOUT register - ERRCTRL_FNMODEOUT
4.4.17. All Alarms After Fault Injection - ERRCTRL_FNGIALARMS
4.4.18. Error Controller Context Register - ERRCTRL_FNGICTXT4
4.4.19. CMP Mismatch CONTEXT Registers - ERRCTRL_FNGICMPCTXT0 … ERRCTRL_FNGICMPCTXT3
4.4.20. STATISTICS registers: ERRCTRL_FNGISTAT0 and ERRCTRL_FNGISTAT4
4.4.21. State register - ERRCTRL_FNPERIPHGI4
1. About the Nios® V Processor Lockstep
Updated for: |
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Intel® Quartus® Prime Design Suite 25.1 |
The Nios® V Processor Lockstep feature utilizes fRSmartComp technology to implement a smart comparator in register transfer level (RTL). Altera utilizes the Dual-Core Lock Step (DCLS) safety architecture to implement the smart comparator. This approach allows for the integration of the technology into the Nios® V/g processor, allowing for the design of fail-safe applications.
Use Case Type | Uses Case | Application Benefit | Standard DCLS | LockStep |
---|---|---|---|---|
Standard | Fail-safe | Fail-safe | √ | √ |
Smart | False Positive Avoidance | Improved Availability | - | |
Fail-safe after Fault Discrimination | - | √ | ||
Fail Safe after Fault Discrimination and Functional Downgrade | - | √ | ||
Timeout on System Reset and Detection | Improved Robustness | - | √ |
Figure 1. Block Diagram of Nios® V Processor Lockstep System
A system supervisor controls the fRSmartComp by managing its configuration and system interface. The system supervisor determines when to activate a safe state or implement other measures to address failures at the system level. The system supervisor can be the host Nios® V processor CPU or an external manager. The Lockstep feature acts as passive diagnostic logic, providing safety features.