Nios® V Processor: Lockstep Implementation User Guide

ID 833274
Date 4/17/2025
Public
Document Table of Contents

1. About the Nios® V Processor Lockstep

Updated for:
Intel® Quartus® Prime Design Suite 25.1
The Nios® V Processor Lockstep feature utilizes fRSmartComp technology to implement a smart comparator in register transfer level (RTL). Altera utilizes the Dual-Core Lock Step (DCLS) safety architecture to implement the smart comparator. This approach allows for the integration of the technology into the Nios® V/g processor, allowing for the design of fail-safe applications.
Table 1.  The Benefits of Safety Use Cases and Comparing Standard DCLS with Lockstep
Use Case Type Uses Case Application Benefit Standard DCLS LockStep
Standard Fail-safe Fail-safe
Smart False Positive Avoidance Improved Availability -  
Fail-safe after Fault Discrimination -
Fail Safe after Fault Discrimination and Functional Downgrade -
Timeout on System Reset and Detection Improved Robustness -
Figure 1. Block Diagram of Nios® V Processor Lockstep System

A system supervisor controls the fRSmartComp by managing its configuration and system interface. The system supervisor determines when to activate a safe state or implement other measures to address failures at the system level. The system supervisor can be the host Nios® V processor CPU or an external manager. The Lockstep feature acts as passive diagnostic logic, providing safety features.