GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.4.1. Testbench Components

Figure 14. Simplex Mode IP Core (Non-DS) Block Diagram
Figure 15. Simplex mode IP core (DS) Block Diagram
Table 10.  Testbench Components
Component Description
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX and video pattern generator blocks.
TX checker This checker verifies if the TX serial data contains a valid TRS signal.
RX checker

This checker detects the trs_locked signal from the RX protocol and compares the actual number of transceiver reconfigurations performed versus the expected number.

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