GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.3.2. Clocking Scheme

Figure 12. Parallel Loopback with Simplex Mode IP Core
Figure 13. Serial Loopback with Simplex Mode IP Core

Section Content
Clocking Scheme Components

Level Two Title