GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.3.1. Design Components

The SDI II Intel FPGA IP core design examples require the following components.

Table 5.  Device Under Test (DUT) ComponentsThe DUTs are RX top, TX top, and Du Top. The DUTs are different if the parameter value is different. For more information about the DUT, refer to the figures in Clocking Scheme.
Component Description
SDI II
  • TX
    • The IP core receives video data from top level and encodes the necessary information, for example line number, CRC or payload ID into the data streams.
  • RX
    • The IP core receives parallel data from Transceiver Native PHY and performs the necessary decoding, such as descrambling, realigning the data, and extracting the necessary information.
    • The output data from these blocks connects to the SDI PHY adapter module before passing it to GTS PMA/FEC Direct PHY Intel® FPGA IP.
GTS PMA/FEC Direct PHY
  • TX
    • Hard transceiver block which receives parallel data from SDI core and serializes the data before transmitting it.
  • RX
    • Hard transceiver block to receive serial data from an external video source.
    • The PHY runs in System PLL clocking mode and system clock output always runs at a higher clock frequency than the native PMA recovered clock.
SDI mode Minimum System PLL Output Frequency
HD-SDI single rate 150 MHz
3G-SDI single rate 300 MHz
12G-SDI single rate 600 MHz
PHY adapter Adapter block which includes DCFIFO for converting the bit width of parallel data between transceiver and SDI core, and to transfer data between these two clock domains.
Table 6.  Loopback Top Components
Component Description
Loopback FIFO This module contains DCFIFO for transfer of video data between receiver clock domain and transmitter clock domain.
Reclock
  • This module is required for the Parallel loopback without external VCXO design for comparing the phase between receiver parallel clock and transmitter parallel clocks.
  • The output interfaces of this block are connected to the reconfiguration Avalon® memory-mapped interface of TX transceiver. If there is any difference in term of frequency between these clock domains, this module generates the necessary signals to reconfigure TX PLL so that both the clock frequencies are as close as possible.
Table 7.  Video Pattern Generator Components
Component Description
Video Pattern Generator Basic video pattern generator which can support SD-SDI up to 12G-SDI video formats with 4:2:2 YCbCr. You can select static video with colorbar pattern or pathological pattern from this pattern generator.
Pattern Gen Control PIO Provides a memory-mapped interface for controlling the video pattern generator.
JTAG to Avalon Master Bridge Provides System Console host access to the Parallel I/O (PIO) IP in the design via the JTAG interface.
Table 8.  Common Blocks at Top Level
Common Block Description
GTS System PLL Clocks FPGA IP

This IP connects the System PLL output clock to the GTS PMA/FEC Direct PHY Intel® FPGA IP.

System PLL clock output is always set to run at a higher clock frequency than the native PMA recovered clock.

SDI mode Minimum System PLL output frequency
HD-SDI single rate 150 MHz
3G-SDI single rate 300 MHz
12G-SDI single rate 600 MHz
GTS Reset Sequencer Intel® FPGA IP

The GTS Reset Sequencer Intel® FPGA IP must be instantiated for each side of the device that uses transceivers.

Refer to Implementing the GTS Reset Sequencer Intel FPGA IP for more information.

System Reset

This module contains Reset Release Intel® FPGA IP to provide a known initialized state for system logic to begin operation. The module also includes a reset delay block to further delay the signal status from the IP for a safer operation.

For more information, refer to Stratix® 10 Reset Release Intel® FPGA IP chapter in the Stratix® 10 Configuration User Guide.

Related Information
Level Two Title