GTS SDI II IP User Guide

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ID 823539
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Quick Reference 2. GTS SDI II IP Core Overview 3. GTS SDI II IP Core Getting Started 4. GTS SDI II IP Parameters 5. GTS SDI II IP Core Functional Description 6. GTS SDI II IP Core Signals 7. GTS SDI II IP Core Design Considerations 8. GTS SDI II IP Core Testbench and Design Examples 9. Document Revision History for the GTS SDI II IP User Guide
2. GTS SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. GTS SDI II IP Core Getting Started x
3.1. Installing and Licensing IP Cores 3.2. Design Walkthrough 3.3. GTS SDI II IP Core Component Files 3.4. Compiling the GTS SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. GTS SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. SMPTE RP168 Switching Support 5.4.2. SD 20-Bit Interface for Dual/Triple Rate 5.4.3. Intel FPGA Video Streaming Interface
5.4.3. Intel FPGA Video Streaming Interface x
5.4.3.1. RGB Pixel Packing 5.4.3.2. YCbCr 444 Pixel Packing 5.4.3.3. YCbCr 422 Pixel Packing 5.4.3.4. Supported Modes
6. GTS SDI II IP Core Signals x
6.1. GTS SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. GTS SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Dual Simplex Merging Tool (DS tool)
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Agilex™ 5 Devices
7.1.1. Handling Transceiver in Agilex™ 5 Devices x
7.1.1.1. System PLL Clocking Mode 7.1.1.2. Unused Transceiver Tiles 7.1.1.3. SmartVID Settings
7.2. Dual Simplex Merging Tool (DS tool) x
7.2.1. Using the DS Tool
8. GTS SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Agilex™ 5 Devices
1. GTS SDI II IP Quick Reference
2. GTS SDI II IP Core Overview
3. GTS SDI II IP Core Getting Started
4. GTS SDI II IP Parameters
5. GTS SDI II IP Core Functional Description
6. GTS SDI II IP Core Signals
7. GTS SDI II IP Core Design Considerations
8. GTS SDI II IP Core Testbench and Design Examples
9. Document Revision History for the GTS SDI II IP User Guide

4. GTS SDI II IP Parameters

Note: For GTS SDI II design example parameters, refer to the respective GTS SDI II design example user guides.
Table 9.  GTS SDI II IP Parameters
Parameter Value Description
Configuration Options
Video standard HD-SDI, 3G-SDI, 12G-SDI, Triple rate (up to 3G-SDI) 4, Multi rate (up to 12G-SDI)4 Sets the video standard.
  • HD-SDI—enables option for in line insertion and extraction and CRC generation and extraction
  • Triple-, or multirate SDI—includes the processing blocks for the respective supported rates. Logics for bypass paths and to automatically switch between the input standards are included.
    Note: Agilex™ 5 device supports a 12G-SDI single rate as a preliminary feature. You must regenerate the IP when the multirate (up to 12G-SDI) feature is enabled.
SD interface bit width 10 Selects the SD interface bit width. Only applicable for triple rate.
Direction Receiver, Transmitter Sets the port direction. The selection enables or disables the receiver and transmitter supporting logic appropriately.
  • Receiver—instantiates the SDI receiver
  • Transmitter—instantiates the SDI transmitter.
Transceiver Options5
Transceiver reference clock frequency

148.5/148.35 MHz,

74.25/74.175 MHz,

Selects the transceiver reference clock frequency.

The 74.25/74.175 MHz option is available only for HD-SDI.

Dynamic TX clock switching

Off, TX PLL switching, TX PLL reference clock switching

  • Off: Disable dynamic switching
  • TX PLL switching: Instantiates two PLLs, each with a reference input clock
  • TX PLL reference clock switching: Instantiates a PLL with two reference input clocks.
Turn on this option to allow dynamic switching between 1 and 1/1.001 data rates.
Receiver Options
Increase error tolerance level On, Off
  • On: Error tolerance level = 15
  • Off: Error tolerance level = 4

Turn on this option to increase the tolerance level for consecutive missed end of active videos (EAVs), start of active videos (SAVs), or erroneous frames.

CRC error output On, Off
  • On: CRC monitoring (Not applicable for SD-SDI mode)
  • Off: No CRC monitoring (saves logic)
Extract Payload ID (SMPTE ST 352) On, Off
  • On: Extract payload ID
  • Off: No payload ID extraction (saves logic)

You must turn on this option for 3G-SDI and HD SDI modes. The extracted payload ID is required for consistent detection of the 1080p format.

Rx core clock (rx_coreclk) frequency 100 MHz to 156.25 MHz Selects the supported clock frequency for the rx_coreclk signal. The default frequency is 148.5/148.35 MHz.
Note: This option is only available in Quartus® Prime Pro Edition software
Note: The frequency range - 100 MHz to 156.25 MHz is available in Agilex™ 5 in the Quartus® Prime Pro Edition software.
Transmitter Options
Insert payload ID (SMPTE ST 352) On, Off
  • On: Insert payload ID
  • Off: No payload ID insertion (saves logic)

Video Streaming Options
Enable active video data protocols None
  • Turn on to enable Intel FPGA video streaming interface.
  • Turn off for clocked video interface.
  • Only available when Video standard is set to Multi rate (up to 12G-SDI)4.
Bits per color sample 12
  • Select the number of bits per color sample.

  • Only available when Enable active video data protocols is set to AXIS-VVP Full.

Wrapper Options
SDI II wrapper BASE only, Both BASE and PHY
  • BASE only: Generate Intel SDI_II IP with Core layer only.
  • Both BASE and PHY: Generate Intel SDI_II IP with both Core and PHY layer.
TX Analog Parameters Options
Spread Spectrum Enable, Disable Specifies whether TX PLL reference clock will be spread spectrum.
Enable TX P&N Invert Enable, Disable Invert TX serial inputs P and N.
TX EQ Post Tap 1 0-19 Post tap 1 coefficient, 1.0 step size.
TX EQ Main Tap 0-55 Main tap coefficient, 1.0 step size.
TX EQ Pre Tap 1 0-15 Pre tap 1 coefficient, 1.0 step size.
TX EQ Pre Tap 2 0-7 Pre tap 2 coefficient, 1.0 step size.
RX Analog Parameters Options
RX Adaptation Mode Manual Specifies type of RX adaptation
  • FLUX_ADAPTATION - Firmware based auto adaptation.
  • MANUAL_ADAPTATION - Firmware based adaptation is disabled and RX analog parameters like vga_gain, hf_boost and dfe_tap_1 are used to tune the RX links.
Enable RX P&N Invert Enable, Disable Invert RX serial inputs P and N.

RX External Coupling Mode

 AC, DC Specifies whether there is a decoupling cap on board or not.
Selects value of RX termination mode Grounded, Differential Specifies how RX is terminated.
Selects value of RX onchip termination R_1(85 ohms), R_2(100 ohms) Enable RX onchip termination.
RX EQ VGA Gain 0-63 RX eq vga gain.
RX EQ High Frequency Boost 0-63 RX eq hf boost.
RX EQ DFE Data Tap1 0-63 RX eq dfe data tap 0.
4 This feature is not supported in the current release.
5 These options are not supported in the current release.
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