AXI Multichannel DMA FPGA IP for PCI Express* Release Notes

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ID 817914
Date 8/04/2025
Public

1.2. AXI Multichannel DMA FPGA IP for PCI Express v3.0.0

Table 2.  v3.0.0 2025.03.31
Quartus® Prime Version Description Impact
25.1 Added support for the AXI-MM user interface for the MCDMA user mode. You can now select the AXI Memory- Mapped interface for the Multichannel DMA user mode.
Added the AXI-MM DMA design example. You can now generate an AXI-MM DMA design example when you select the AXI-MM user interface for MCDMA mode.
Added the AXI-MM Traffic Generator/Checker design example. You can now generate an AXI-MM Traffic Generator/Checker design example when you select the BAM+BAS mode.
Added the AXI-MM BAM EP Memory design example. You can now generate an AXI-MM BAM EP Memory design example when you select the Bursting Master mode.
Added the Packet Loopback design example support for the BAM+MCDMA and BAM+BAS+MCDMA modes. You can now generate an AXI-S Device-side Packet Loopback design example when you select the AXI-S interface for MCDMA.
Removed support for the Gen4 1x16 1024-bit data width. Gen4 1x16 now only supports the 512-bit data width.
Removed support for the Gen4 1x8 512-bit data width. Gen4 1x8 now only supports the 256-bit data width.
Added support for the Agilex™ 7 I-Series ES2 and Production Development Kits in the Example Designs tab. You can now target the Agilex™ 7 I-Series ES2 and Production Development Kits when you generate a design example.
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