AXI Multichannel DMA FPGA IP for PCI Express* Release Notes

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ID 817914
Date 8/04/2025
Public

1.1. AXI Multichannel DMA FPGA IP for PCI Express v3.1.0

Table 1.  v3.1.0 2025.07.21
Quartus® Prime Version Description Impact
25.1.1 Added the AXI-S Packet Generate/Check design example. You can generate the AXI-S Packet Generate/Check design example when you select the AXI-S user interface for DMA.
Updated the IP name per the rebranding guidelines of Altera. The IP name has been changed to AXI Multichannel DMA FPGA IP for PCI Express.
Level Two Title