AXI Multichannel DMA FPGA IP for PCI Express* Release Notes

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ID 817914
Date 8/04/2025
Public

1.4. AXI Multichannel DMA FPGA IP for PCI Express v2.0.0

Table 4.  v2.0.0 2024.07.22
Quartus® Prime Version Description Impact
24.2 Added support for AXI Streaming Device-side Packet Loopback design example.

You can generate an AXI Streaming Device-side Packet Loopback design example, generate the bitstream, and perform a hardware test.

Note: Design example simulation and full timing closure are not supported in the current release.
Level Two Title