AXI Multichannel DMA FPGA IP for PCI Express* Release Notes

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ID 817914
Date 8/04/2025
Public

1.3. AXI Multichannel DMA FPGA IP for PCI Express v2.2.0

Table 3.  v2.2.0 2025.01.13
Quartus® Prime Version Description Impact
24.3.1 Added 2x8 design example support. To generate a 2x8 design example:
  1. Select the IP PCIe Mode: 1x8.
  2. Select the design example PCIe Mode: 2x8.
 You can generate a 2x8 example design.
Note: 1x8 design example generation is not supported in the current release.
Added 1x4 IP support. You can generate a 1x4 IP by creating a quartus.ini file with a line: ini_guard=on.
Note: x4 design example generation is not supported in the current release.
1x8 IP generation requires a special Quartus initialization file (quartus.ini) in the Quartus project directory. You need to create the quartus.ini file with a line: ini_guard=on.
Design examples support only hardware testing in the current release. Support for design example simulation is not available in the current release.
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