GTS CPRI PHY IP Design Example User Guide

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ID 814583
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide

2.5. Interface Signals

Table 22.  Design Example Interface Signals
Signal Direction Description
ref_clk100MHz Input Input clock for CSR access on all the reconfiguration interfaces. Drive at 100 MHz.
i_clk_ref[0] Input Reference clock for System PLL. Drive at 153.6 MHz.
i_clk_ref[1] Input Transceiver reference clock. Drive at:
  • 153.6 MHz for CPRI line rates 1.2, 2.4, 3, 4.9, 6.1, and 9.8 Gbps.
  • 184.32 MHz for CPRI line rates 10.1, 12.1, and 24.3 Gbps without RS-FEC.
  • 122.88 MHz for all CPRI line rates.
i_rx_serial[n] Input Transceiver PHY input serial data.
o_tx_serial[n] Output Transceiver PHY output serial data.
Level Two Title