GTS CPRI PHY IP Design Example User Guide

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ID 814583
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY IP Design Example User Guide Archives 4. Document Revision History for GTS CPRI PHY IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY IP Design Example User Guide Archives
4. Document Revision History for GTS CPRI PHY IP Design Example User Guide

2.4. Hardware Design Example

Figure 8. Block Diagram for Basic CPRI Mode Hardware Design Example
The GTS CPRI PHY IP core hardware design example includes the following components:
  • GTS CPRI PHY IP core.
  • Packet client logic block that generates and receives traffic.
  • Round trip counter.
  • IOPLL to generate the sampling clock for deterministic latency logic inside the IP, and the round trip counter component at testbench.
  • System PLL to generate the system clocks for the IP.
  • Avalon® memory-mapped address decoder to decode reconfiguration address space for CPRI PHY Reconfiguration Interface, PMA Avalon® Memory-Mapped Interface, and Datapath Avalon® Memory-Mapped Interface.
  • Sources and probes for asserting resets and monitoring the clocks and a few status bits.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.
  • GTS Reset Sequencer IP together with the Soft Reset Controller (SRC) handles all non-PCIe reset scheduling and sequencing for the Agilex™ 5 FPGA.
Figure 9. Block Diagram for Dynamic Reconfiguration Hardware Design Example


Dynamic Reconfiguration Hardware Flow for Design Example

Use the following hardware flow for dynamic reconfiguration of the design example:

  1. Enable the packet round-trip measurement.
    1. Perform the deterministic latency test flow.
    2. Print the deterministic latency data to det_latency.log file.
  2. Power up the CPRI PHY Multirate IP DUT based on profile 0 (9.8G).
  3. Initialize the following testbench variables based on power-up profile:
    • cpri_speed—specifies the speed of the current profile.
    • enable_rsfec—specifies whether RS-FEC is enabled or disabled for the current profile.
    • current_dr_profile—specifies the ID of the current profile.
  4. Perform dynamic reconfiguration.
  5. Check the testbench error flag and determine whether testbench passed or failed.

    This error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.

For customization, you can modify the DR_TRANSITION array variable in src or parameter file to configure the test flow. The Profile ID is passed into the Dynamic Reconfiguration IP to configure the intended dynamic reconfiguration task.

  • DR_TRANSITION—the intended dynamic reconfiguration sequence array. The size of this array variable determines the number of dynamic reconfigurations performed. For example, given that the design example has the following profiles:
    set DR_PROFILE(1) DR_9P8G
set DR_PROFILE(2) DR_6G
set DR_PROFILE(3) DR_4P9G
set DR_PROFILE(4) DR_3G
set DR_PROFILE(5) DR_2P4G
set DR_PROFILE(6) DR_1P2G

    You want to achieve the following dynamic reconfiguration sequence:

    9.8G ->6G-> 4.9G->3G->2.4G->1.2G->9.8G

    The variables changes are:

    set DR_TRANSITION(1) 2
set DR_TRANSITION(2) 3
set DR_TRANSITION(3) 4
set DR_TRANSITION(4) 5
set DR_TRANSITION(5) 6
set DR_TRANSITION(6) 1
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