GTS CPRI PHY IP Design Example User Guide

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ID 814583
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY IP Design Example User Guide Archives 4. Document Revision History for GTS CPRI PHY IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY IP Design Example User Guide Archives
4. Document Revision History for GTS CPRI PHY IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 25.1.1
IP Version 8.0.0

The GTS CPRI PHY IP provides a simulation testbench and hardware design example that supports compilation and hardware testing (when you select Basic for CPRI Mode). When you select Dynamically reconfigurable, the design example supports all CPRI rates for simulation, and supports 9.8G and below for hardware. When you generate the design example, the IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Altera also provides a compilation-only example project that you can use to quickly estimate IP area and timing.

The GTS CPRI PHY IP allows you to generate design examples for all supported combinations of CPRI channels and CPRI line bit rates. The testbench and design example support multiple parameter combinations of the GTS CPRI PHY.

Figure 1. Development Steps for the Design Example

Section Content
Hardware and Software Requirements
Generating the Design
Directory Structure
Simulating the Design Example Testbench

Level Two Title