GTS CPRI PHY IP Design Example User Guide

Download PDF
ID 814583
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY IP Design Example User Guide Archives 4. Document Revision History for GTS CPRI PHY IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY IP Design Example User Guide Archives
4. Document Revision History for GTS CPRI PHY IP Design Example User Guide

2.2.8. Reset Sequencer

You must instantiate the GTS Reset Sequencer IP for each side of the device that uses transceivers. This is a mandatory IP required for simulation and proper device operation of the Agilex™ 5 FPGA.

Level Two Title