GTS CPRI PHY IP User Guide

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ID 814577
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY FPGA IP 2. Getting Started 3. GTS CPRI PHY IP Parameters 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. GTS CPRI PHY Intel FPGA IP User Guide Archives 9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide
1. About the GTS CPRI PHY FPGA IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing IPs 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing IPs x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameters x
3.1. GTS CPRI PHY IP Parameters: IP Tab 3.2. GTS CPRI PHY IP Design Example Parameters 3.3. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement 4.3. Dynamic Reconfiguration
4.2. Latency Measurement x
4.2.1. Deterministic Latency
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Dynamic Reconfiguration Local Avalon Memory-Mapped Interface 5.12. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY FPGA IP
2. Getting Started
3. GTS CPRI PHY IP Parameters
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. GTS CPRI PHY Intel FPGA IP User Guide Archives
9. Document Revision History for the GTS CPRI PHY Intel FPGA IP User Guide

5.11. GTS CPRI PHY IP Dynamic Reconfiguration Local Avalon Memory-Mapped Interface

The IP has n sets of local Avalon Memoryy-Mapped interfaces for n transceiver channels. This interface allow you to dynamically change the Agilex 5 integrated transceiver subsystem and to reconfigure the source.

The Avalon Memory-Mapped interfaces on the IP use 21-bit addresses to allow you to use the same interface for the global Avalon Memory-Mapped interface. However, only 20 bits are in use for local interfaces. The dynamic reconfiguration controller uses 21 bits (the same number of bits that the generated IP uses). The IP drives the MSB with a fixed 0 directly on the output and the IP uses only 20 bits internally. The signal names matches the names on the generated IP (even though it does not match the Avalon Interface Specification) to ease connections between the blocks. Connect these signals directly to the matching ports on the generated IP. The Nios V processor only performs 32-bit accesses, so IP drives the byte enables to fixed values directly on the outputs.

To allow easy arbitration between local Avalon Memory-Mapped interfaces, drive all outputs to 0 in all cycles when no transaction is pending.

Table 27.  GTS CPRI PHY IP Dynamic Reconfiguration Local Avalon Memory-Mapped Interface
Name Width Domain Description
i_dr_lavmm_addr_ch0 21 i_dr_lavmm_clk_ch0 Address for local Avalon Memory-Mapped target interfaces.
i_dr_lavmm_read_ch0 1 i_dr_lavmm_clk_ch0 Read command for local Avalon Memory-Mapped target interfaces
i_dr_lavmm_write_ch0 1 i_dr_lavmm_clk_ch0 Write command for local Avalon Memory-Mapped target interfaces
o_dr_lavmm_rdata_ch0 32 i_dr_lavmm_clk_ch0 Read data from reads to local Avalon Memory-Mapped target interfaces
o_dr_lavmm_rdata_valid_ch0 1 i_dr_lavmm_clk_ch0 Read data from local Avalon Memory-Mapped target interfaces is valid
i_dr_lavmm_wdata_ch0 32 i_dr_lavmm_clk_ch0 Data for writes to local Avalon Memory-Mapped target interfaces
o_dr_lavmm_waitreq_ch0 1 i_dr_lavmm_clk_ch0 Local Avalon Memory-Mapped interfaces stalling signal for operations on local Avalon Memory-Mapped target interfaces
i_dr_lavmm_be_ch0 4 i_dr_lavmm_clk_ch0 Byte enable for local Avalon Memory-Mapped target interfaces
Level Two Title