GTS CPRI PHY IP User Guide

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ID 814577
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY IP 2. Getting Started 3. GTS CPRI PHY IP Parameters 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. Document Revision History for the GTS CPRI PHY IP User Guide 9. GTS CPRI PHY IP User Guide Archives
1. About the GTS CPRI PHY IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Altera® IP 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Altera® IP x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameters x
3.1. GTS CPRI PHY IP Parameters: IP Tab 3.2. GTS CPRI PHY IP Design Example Parameters 3.3. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency for GTS CPRI PHY IP
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Dynamic Reconfiguration Local Avalon Memory-Mapped Interface 5.12. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY IP
2. Getting Started
3. GTS CPRI PHY IP Parameters
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. Document Revision History for the GTS CPRI PHY IP User Guide
9. GTS CPRI PHY IP User Guide Archives

2.1. Installing and Licensing Altera® IP

The Quartus® Prime Pro Edition software installation includes the Altera® IP library. This library provides many useful IP for your production use without the need for an additional license. Some Altera® IP cores require purchase of a separate license for production use. The Altera® FPGA IP Evaluation Mode allows you to evaluate these licensed IP in simulation and hardware, before deciding to purchase a full production IP license. You only need to purchase a full production license for licensed Altera® IP after you complete hardware testing and are ready to use the IP in production.

The Quartus® Prime software installs IP in the following locations by default:

Figure 1. IP Core Installation Path


Table 5.  IP Core Installation Locations
Location Software Platform
<drive>:\altera_pro\quartus\ip\altera Quartus® Prime Pro Edition software Windows*
<home directory>:/altera_pro/quartus/ip/altera Quartus® Prime Pro Edition software Linux*

Section Content
Intel FPGA IP Evaluation Mode

Level Two Title