GTS CPRI PHY IP User Guide

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ID 814577
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY IP 2. Getting Started 3. GTS CPRI PHY IP Parameters 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. Document Revision History for the GTS CPRI PHY IP User Guide 9. GTS CPRI PHY IP User Guide Archives
1. About the GTS CPRI PHY IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Altera® IP 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Altera® IP x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameters x
3.1. GTS CPRI PHY IP Parameters: IP Tab 3.2. GTS CPRI PHY IP Design Example Parameters 3.3. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency for GTS CPRI PHY IP
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Dynamic Reconfiguration Local Avalon Memory-Mapped Interface 5.12. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY IP
2. Getting Started
3. GTS CPRI PHY IP Parameters
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. Document Revision History for the GTS CPRI PHY IP User Guide
9. GTS CPRI PHY IP User Guide Archives

3.2. GTS CPRI PHY IP Design Example Parameters

Table 8.  GTS CPRI PHY IP Design Example Parameters
Parameter Values Description
Select design

Single instance of IP core (default),

Four instances of IP core

 The design example instantiates a single or four instances of the IP to demonstrate multichannel CPRI PHY.
Simulation 0, 1 (default) When you turn on Simulation, Quartus Prime generates all necessary files required for simulation.
Synthesis 0, 1 (default) When you turn on Synthesis, Quartus Prime generates all necessary files required for synthesis.
Generate file format Verilog, VHDL

Select the HDL format for the generated IP files in the design example. For VHDL, only the Platform Designer generated wrapper of various IPs within the design are in VHDL format. The other files such as testbench and design example components remain as Verilog HDL.
Select board None,

Agilex 5 E-Series 065B Premium Development Kit (ES1)

 Select your development kit. If this menu is gray, no board is supported for the options you selected. For example Synthesis is off. If you select a development board, the target device for generation matches the device on the development kit.
Select device initialization clock

OSC_CLK_1_25MHZ

OSC_CLK_1_100MHZ

OSC_CLK_1_125MHZ (default)

 This option provides support for device initialization clock setting in the design example. The development kit only supports OSC_CLK_1_125MHZ. If you are using a different development kit board, refer to the specifications of the board and select the correct option from the menu. Failure to select the correct frequency might give incorrect hardware behavior.
Figure 5. Example Design Tab in IP Parameter Editor


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