GTS CPRI PHY IP User Guide

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ID 814577
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY IP 2. Getting Started 3. GTS CPRI PHY IP Parameters 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. Document Revision History for the GTS CPRI PHY IP User Guide 9. GTS CPRI PHY IP User Guide Archives
1. About the GTS CPRI PHY IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Altera® IP 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Altera® IP x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameters x
3.1. GTS CPRI PHY IP Parameters: IP Tab 3.2. GTS CPRI PHY IP Design Example Parameters 3.3. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency for GTS CPRI PHY IP
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Dynamic Reconfiguration Local Avalon Memory-Mapped Interface 5.12. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY IP
2. Getting Started
3. GTS CPRI PHY IP Parameters
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. Document Revision History for the GTS CPRI PHY IP User Guide
9. GTS CPRI PHY IP User Guide Archives

1.1. GTS CPRI PHY IP Features

  • Compliant with the CPRI Specification V7.0 (2015-10-09).
  • Dynamic reconfiguration example design simulation and hardware support for CPRI rate of 9.8304 Gbps and lower.
  • Dynamic reconfiguration example design simulation support for CPRI rate of 24.33024Gbps and lower.
  • Static line bit rates of:
    • 1.228 Gbps
    • 2.4576 Gbps
    • 3.072 Gbps
    • 4.9152 Gbps
    • 6.144 Gbps
    • 9.8304 Gbps
    • 10.1376 Gbps with or without RS-FEC
    • 12.16512 Gbps with or without RS-FEC
    • 24.33024 Gbps with or without RS-FEC
  • Deterministic latency measurement.
  • Register access interface to external or on-chip processor, using the Altera® Avalon® memory-mapped interconnect specification.
  • Physical medium attachment (PMA) adaptation.
Table 1.  Available Line Rates
CPRI Line Bit Rate (Gbps) RS-FEC Support Dynamic Reconfiguration Reference Clock (MHz)

Deterministic Latency Support
1.2288 No Yes 153.6 or 122.88 Yes
2.4576 No Yes 153.6 or 122.88 Yes
3.072 No Yes 153.6 or 122.88 Yes
4.9152 No Yes 153.6 or 122.88 Yes
6.144 No Yes 153.6 or 122.88 Yes
9.8304 No Yes 153.6 or 122.88 Yes
10.1376 Without No 184.32 or 122.88 Yes
12.16512 Without No 184.32 or 122.88 Yes
24.33024 Without No 184.32 or 122.88 Yes
10.1376 With No 184.32 or 122.88 Yes
12.16512 With No 184.32 or 122.88 Yes
24.33024 With No 184.32 or 122.88 Yes
Level Two Title