GTS CPRI PHY IP User Guide

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ID 814577
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS CPRI PHY IP 2. Getting Started 3. GTS CPRI PHY IP Parameters 4. Functional Description 5. Interface Signals 6. GTS CPRI PHY IP Registers 7. GTS CPRI PHY IP Troubleshooting 8. Document Revision History for the GTS CPRI PHY IP User Guide 9. GTS CPRI PHY IP User Guide Archives
1. About the GTS CPRI PHY IP x
1.1. GTS CPRI PHY IP Features 1.2. GTS CPRI PHY IP Device Family Support 1.3. GTS CPRI PHY IP Device Speed Grade Support 1.4. GTS CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Altera® IP 2.2. Specifying the GTS CPRI PHY IP Parameters and Options 2.3. Generated File Structure 2.4. GTS CPRI PHY IP Testbenches
2.1. Installing and Licensing Altera® IP x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Specifying the GTS CPRI PHY IP Parameters and Options x
2.2.1. System PLL Clock for Your IP Design
3. GTS CPRI PHY IP Parameters x
3.1. GTS CPRI PHY IP Parameters: IP Tab 3.2. GTS CPRI PHY IP Design Example Parameters 3.3. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency for GTS CPRI PHY IP
5. Interface Signals x
5.1. GTS CPRI PHY IP Clock Signals 5.2. GTS CPRI PHY IP Reset Signals 5.3. GTS CPRI PHY IP TX MII (64b/66b) 5.4. GTS CPRI PHY IP RX MII (64b/66b) 5.5. GTS CPRI PHY IP Status Interface for 64b/66b Line Rate 5.6. GTS CPRI PHY IP TX Interface (8b/10b) 5.7. GTS CPRI PHY IP RX Interface (8b/10b) 5.8. GTS CPRI PHY IP Status Interface for 8b/10b Line Rate 5.9. GTS CPRI PHY IP Serial Interface 5.10. GTS CPRI PHY Reconfiguration Interface 5.11. GTS CPRI PHY IP Dynamic Reconfiguration Local Avalon Memory-Mapped Interface 5.12. GTS CPRI PHY IP Datapath and PMA Avalon Memory-Mapped Interface
5.1. GTS CPRI PHY IP Clock Signals x
5.1.1. GTS CPRI PHY IP Required Clock Frequencies
1. About the GTS CPRI PHY IP
2. Getting Started
3. GTS CPRI PHY IP Parameters
4. Functional Description
5. Interface Signals
6. GTS CPRI PHY IP Registers
7. GTS CPRI PHY IP Troubleshooting
8. Document Revision History for the GTS CPRI PHY IP User Guide
9. GTS CPRI PHY IP User Guide Archives

7. GTS CPRI PHY IP Troubleshooting

Why does GTS CPRI PHY IP Example Design give an error with 24G or 12G rates in the Quartus® Prime Pro Edition software version 24.3?

Because of a problem in the Quartus® Prime Pro Edition software version 24.3, the IP parameter editor allows you to generate an Example Design with 24G and 12G rates, even though the Agilex™ 5 E-Series device does not support 24G and 12G data rates. Unfortunately, the IP parameter editor does not prevent generation of these configurations.

  • Avoid this problem by selecting only 10G or below rate when generating the GTS CPRI PHY IP Example Design.
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