Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 10/10/2025
Public
Document Table of Contents

11.5.1. FPGA-to-HPS Bridge

The FPGA-to-HPS (F2H) bridge provides a cache-coherent memory access path from an FPGA manager to HPS resources, such as DDR and OCRAM. This bridge consists of a single physical ACE5-Lite 256-bit non-configurable interface.
Note: The HPS F2H interface has a fixed data size of 256-bits. This interface allows for narrow burst sizes less than 256-bits However, if a fabric initiator generates a transfer narrower than the interface width (i.e., less than the 256-bits wide data and a non-zero burst size), there is no guarantee that the HPS F2H interface will respond with narrower data aligned on non-256-bit boundaries of the 256-bit data bus. For example, if ARADDR = 0x0010_0000, ARSIZE = 0x4, and ARLEN = 0x3, the HPS F2H interface returns two beats of 32 bytes per beat followed by two null cycles, instead of four beats of 16 bytes per beat. Altera recommends that you add width adaptation interconnect logic between the fabric initiator and the HPS F2H interface to ensure that the narrow-width data is packed/unpacked properly.

The figure below shows the F2H block diagram.

Figure 289. F2H Block Diagram

The following table shows the F2H bridge signals.

Table 323.  F2H Bridge Signals
Name Direction Description
fpga2hps_clock Input

Clock from a single source in the FPGA.

fpga2hps_reset Input

Async active high reset to the bridge.

Note: h2f_reset signal must be connected to fpga2hps_reset signal for proper bridge operation.

The following table lists the properties of the F2H bridge, including the interface exposed to the FPGA fabric.

Table 324.  F2H Bridge Properties
Bridge Property Value
Protocol AMBA 5 ACE5-Lite38
Clock fpga2hps_clock (from FPGA)
Data width 256-bit
Address width 40-bit
ID width 5-bit
Fixed burst No
Min narrow burst size 1 byte
Max wrap burst length 16
Read interleaving Yes
Ready latency requirement Yes
A*Region Width 0
A*Len Width 7 (256)
A*QoS Width 4
nPendingTrans (Issuance/Acceptance) 16
nPendingOrderID 16
38 You can use the Altera ACE5-Lite Cache Coherency Translator IP to connect any AXI or Avalon® memory-mapped FPGA Manager in the fabric to the F2H bridge. For more information about this IP, refer to the Embedded Peripherals IP User Guide .